Research on the Application of Micro-Program Controller in Parallel Neural Networks

Abstract:

In this paper a pipelined array of neurons based on the micro-program controller is proposed as the BP network control circuit implementations, without changing the hardware circuit under the premise of the way by increasing the instruction to meet the BP neural network parallel computing applications to enhance the flexibility of hardware.

• Periodical: Advanced Materials Research (Volumes 271-273)
• Pages: 1023-1028
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.271-273.1023
• Online since: July 2011
• Authors: Xi Huang, Ping Wang, Zong Huang Weng, Xiao Zhang, Wei Han Zhong
• Keywords: Field-Programmable Gate Array (FPGA), Micro-Program Controller, Neural Network (NN)

References

[1] Li Ang, Wang Qin, Li Zhancai and Wan Yong, The Implementation Method of Neural Network Hardware Based on FPGA, The Journal of University of Science and Technology Beijing, 29 (1), pp.90-95, (2007).

[2] Zhang Fangfang, He Juan and Li Mingjun. The Research Summary of BP Learning Algorithm Based on Derivative Optimization, The Application Research of Computers, 26 (3), pp.809-813, (2009).

[3] Han Liqun, Artificial Neural Network Tutorial, Beijing University of Posts and Telecommunications Press, 5, 34-38, 64, p.247., (2006).

[4] Zhu Daqi and Shi Hui, The Principle and Application of Artificial Neural Networks, Beijing: Science Press, pp.37-39, (2006).