An Application on Controller to Improve Performance of Multi-Core Shared Memory Based on Network Processing

Article Preview

Abstract:

An application to improve the performance of Multi-Core shared memory based on network processing is described in this paper. In order to get more instructions with address relevancy, the function of chain is applied on the design of SDRAM controller. The application of chain needs to rely on the design of arbitration and command control logic. Firstly, the algorithm of the arbitration is adapted to ensure the function of chain bit. Secondly the command control logic is also optimized to support addressing SDRAM memory efficiently. The verified results show that the efficiency of the SDRAM memory can be improved nearly 47.4% after exploiting more instructions with address relevancy.

You might also be interested in these eBooks

Info:

Periodical:

Advanced Materials Research (Volumes 403-408)

Pages:

2107-2110

Citation:

Online since:

November 2011

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2012 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] W. Eatherton, Router/Swithch Architecture with Networking Specific Memories, Proc. Memory, storage, and serial Interface Technology Conf. (MemCon 2002), Oct. (2002).

Google Scholar

[2] Niraj Shah. Understanding Network Processors. Master's thesis, University of California, Berkeley, 2001-09.

Google Scholar

[3] Lin Weifen, Reinhardt S K, Burger D. Reducing DRAM Latencies with an Integrated Memory Hierarchy Design [C]. Proceedings of the Seventh International Symposium on High Performance Computer Architecture, 2001, 01: 301-312.

DOI: 10.1109/hpca.2001.903272

Google Scholar

[4] S. Iyer, R.R. Kompella, and N. McKeown. Analysis of a memory architecture for fast packet buffers. In Proc. IEEE Workshop High Performance Switching and Routing(HPSR), (2001).

DOI: 10.1109/hpsr.2001.923663

Google Scholar

[5] Huang. F-M, Chen. C-H, Memory access scheduling and bank precharge strategies, 12th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, (2004).

Google Scholar