A Storage Scheme for Fast Packet Buffers in Network Processor

Abstract:

With the Internet services increased explosively, the requirement for network bandwidth is rigorous. Upon the extraordinary development of process capability, Memory access control has become a key factor that impacts the performance of network processor. The paper proposed a storage management for fast packet buffers in network processor, which can enhance the utilization of bandwidth. Experiment results shows that this approach improved the rates of accessing to memory system in network processor remarkably.

• Periodical: Advanced Materials Research (Volumes 403-408)
• Pages: 2628-2631
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.403-408.2628
• Online since: November 2011
• Authors: Jiang Yi Shi, Kun Chen, Kang Li, Zhi Xiong Di
• Keywords: Network Processor, Packet Buffers, Storage Schemes

References

[1] Jorge Garcı´a-Vidal, Member, IEEE, Maribel March, Llorenc¸ Cerda` , Member, IEEE, Jesu´s Corbal, and Mateo Valero, Fellow, IEEE: A DRAM/SRAM Memory Scheme for Fast Packet Buffers IEEE TRANSACTIONS ON COMPUTERS, VOL. 55, NO. 5, MAY (2006).

DOI: 10.1109/tc.2006.63

[2] J. Garcı´a, J. Corbal, L. Cerda`, and M. Valero, Design and Implementation of High-Performance Memory Systems for Future Packet Buffers Proc. MICRO '03, Dec. (2003).

DOI: 10.1109/micro.2003.1253211

[3] S. Iyer, R. Kompella, and N. McKeown, Designing Buffers for Router Line Cards, Technical Report TR02-HPNG-031001, Stanford Univ., Nov. 2002, http: /klamath. stanford. edu/ ~sundaes/publications. html.

[4] Jahangir Hasan Satish Chandra1 T. N. Vijaykumar : Efficient Use of Memory Bandwidth to Improve Network Processor Throughput Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA'03)1063-6897/03 $17. 00 © 2003 IEEE.

DOI: 10.1109/isca.2003.1207009