A Study Using a Risc Core for 100 Gbps Ethernet Network Interfaces

Abstract:

The performance of the current and the next generation server applications such as E-Commerce, Storage and Web server that employ TCP/IP and UDP/IP as the communication protocol of choice depends upon the efficiency of the Protocol Stack Processing within this node. As the speed of networks exceeds one GBPS, the design and implementation of high-performance Network Interfaces (NI) for servers become very challenging. It is observed that using programmable NI with a general purpose processing core to offload some of the TCP/IP or UDP/IP protocol functions can deliver some important features which include scalability, short development times and reduced costs. In this paper, we proposes a new NI-programmable based model that support the Large Segment Offload (LSO) for sending side and a novel technique called Receiving Side Amalgamating (RSA) for receiving side and which is used for incoming packets. The core engine assigned to handle these functions is single specialized embedded processors utilizing RISC cores in each side. As a result, a 240 MHz RISC core can be used in Ethernet Network Interface ENI card for wide range of transmission line speed up to 100 Gbps. These results are based on the use of a specialized RISC core that we developed and simulated. Also, the author has discussed some of the design issues that are related to RISC core based NI and the data movement type.

• Periodical: Advanced Materials Research (Volumes 403-408)
• Pages: 522-531
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.403-408.522
• Online since: November 2011
• Authors: M Elbeshti, M Dixon
• Keywords: Ethernet Netwrok Interface, LSO, Receive Side Amalamate, RISC

References

[1] G. Held. Ethernet Networks (4th ed. ), Design, Implantation, Operation and Management. John Wiley publisher LTD, (2003).

[2] R. Westrelin, N. Fugier, E. Nordmark, K. Kunze, and E. Lemoine, Studying Network Protocol Offload with Emulation: Approach and Preliminary Results, In 12th Annual IEEE Symposium on High Performance Interconnects, Stanford, CA, Aug (2004).

DOI: 10.1109/conect.2004.1375208

[3] P. Shivam and J. S. Chase, On the elusive benefits of protocol offload, In ACM SigComm Workshop on Network-IO Convergence (NICELI), Germany, August (2003).

DOI: 10.1145/944747.944750

[4] H.  Jin and C. Yoo. Impact of protocol overheads on network throughput over high-speed interconnects: measurement, analysis, and improvement., Journal of Supercomputing, Volume 41, Number 1 / July, (2007).

DOI: 10.1007/s11227-007-0101-0

[5] G. Reginier, et al., TCP Onloading for data center servers, IEEE Computer journal , pp.48-58. November, (2004).

[6] Makineni, S., Iyer, R., Sarangam, P., Newell, D., Zhao, L., Illikkal, R., Moses, J. Receive Side Coalescing for Accelerating TCP/IP Processing, In: Robert, Y., Parashar, M., Badrinath,R., Prasanna, V.K. (eds. ) HiPC 2006. LNCS, vol. 4297, pp.289-300. Springer, Heidelberg(2006).

DOI: 10.1007/11945918_31

[7] P. Govindarajan et al. Achieving 10Gbps Network Processing: Are We There Yet?, High Performance Computing – HiPC. Pp 518-528 (2008).

DOI: 10.1007/978-3-540-89894-8_45

[8] P. Willmann, K. Hyong-youb, S. Rixner and S. Pai, An Efficient Programmable 10 Gigabit Ethernet Network Interface Card, " Proceedings of the 11th Int, l Symposium on High-Performance Computer Architecture November (2005).

DOI: 10.1109/hpca.2005.6

[9] H. Kim, Improving Networking Server Performance with Programmable Network Interfaces, " RICE University, Master, s thesis, April, (2003).

[10] T. Mohsenin, Design and Evaluation of FPGA-Based Gigabit- Ethernet/PCI Network Interface Card, " Rice University, Master, s thesis, April (2004).

[11] X. Yang, D. Wu and N. Sun. Design of NIC Based on I/O Processor for Cluster Interconnect Network, Networking, Architecture, and Storage, pp.3-8 July (2007).

DOI: 10.1109/nas.2007.19

[12] T. Henriksson, Intra-Packet Data-Flow Protocol Processing, PhD Dissertation, Linkoping university, (2003).

[13] Aravind Menon and Willy Zwaenepoel. Optimizing TCP receive performance. In USENIX Annual Technical Conference, June (2008).

[14] Elkeelany, On chip novel video streaming system for bi-network, multicasting protocols, Integration, the VLSI Journal, v. 42 n. 3, pp.356-366, June, (2009).

DOI: 10.1016/j.vlsi.2008.10.001

[15] Alacritech SLIC: A Data Path TCP Offload methodology, http: /www. alacritech. com/html/techreview. html.

[16] Y. Hoskote, et al., A 10 GHz TCP Offload Accelerator for 10 Gb/s Ethernet in 90nm Dual-Vt CMOS, IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, (2003).

DOI: 10.1109/isscc.2003.1234292

[17] Leonid Grossman. Large Receive Offload implementation in Neterion 10GbE Ethernet driver. In Ottawa Linux Symposium (OLS), (2005).

[18] Earls, TCP Offload Engines Finally Arrive, Storage Magazine, March (2002).

[19] D. Clark, V. Jacobson, J. Romkey, and H. Salwen. An Analysis of TCP Processing Overhead, IEEE Communications Magazine, 27(6), June (1989).

DOI: 10.1109/35.29545

[20] Leonid Grossman. Large Receive Offload implementation in Neterion 10GbE Ethernet driver. In Ottawa Linux Symposium (OLS), (2005).

[21] Inte, Intel® X38 Express Chipset, (2009).

[22] Y. Hoskote et al., A TCP Offload Accelerator for 10 Gb/s Ethernet in 90-nm CMOS, IEEE Journal of Solid-State Circuits, 38(11): 1866–1875, Nov. (2003).

DOI: 10.1109/jssc.2003.818294

[23] K. Kant TCP offload performance for font-end server, Proc, IEEE Global telecommunications conference (GLOBECOM 03) , IEEE press, 2003 pp.3242-3247.

DOI: 10.1109/glocom.2003.1258835

[24] Interrupt Moderation Using Intel® GbE Controllers 2007. download. intel. com/design/network/applnotsap450. pdf.

[25] N. Tredennick and B. Shimamoto, Go Reconfigure, Special report in IEEE Spectrum, pp.36-41, December (2003).

[26] J. B. Postel, Transmission Control Protocol TCP, RFC 793, Information Sciences Institute, Sept. (1981).

[27] Microsoft Receive-Side Scaling Enhancements in Windows Server 2008, Nov. 2008, www. microsoft. com/whdc/device/network/NDIS_RSS. mspx.

[28] S. Pai and S. Rixner, Exploiting task-level Concurrency in a Programmable Network Interface, Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming, pp.61-72, (2003).

DOI: 10.1145/781498.781506

[29] . Kumar, A.  Huggahalli, R.  Makineni, S. Characterization of Direct Cache Access on multi-core systems and 10GbE.  High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium p.341 – 352 Feb. (2009).

DOI: 10.1109/hpca.2009.4798271

[30] S. Pai and S. Rixner, Exploiting task-level Concurrency in a Programmable Network Interface, Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming, pp.61-72, (2003).

DOI: 10.1145/781498.781506

[31] A MIPS32 Simulator 2101,. http: /pages. cs. wisc. edu/~larus/spim. html.

[32] D. Patterson and J. Hennessy, Computer Organization and Design, The Hardware/Software Interface. Morgan Kaufmann, Los Altos, CA (1998).

[33] S. Senapathi and R. Hernandez, TCP Offload Engines, Network AND Communications magazine pp.103-107 , 2004.

[34] Dragan Stancevic, Zero copy I: user-mode perspective, Linux Journal, Volume 3, Issue 105 (January 3), (2003).

[35] J. Mogul, TCP Offload Is a Dumb Idea Whose Time Has Come, Proc. 9th Workshop on Hot Topics in Operating Systems (HotOS IX), Usenix Assoc., 2003; www. usenix. org/events/hotos03/tech/full_papers/mogul/mogul. pdf.

DOI: 10.1109/hotos.1995.513471

[36] Cardona et al. System Load Based Dynamic Segmentation for Network Interface Cards., Patent US20080295098. Nov. 27, (2008).