Digitally Assisted Backend Correction Pipeline ADC Verilog-A Modeling

Yue Hong Gong; Min Luo; Jian Guo Ma

doi:10.4028/www.scientific.net/AMR.457-458.1122

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 457-458Digitally Assisted Backend Correction Pipeline ADC...

Digitally Assisted Backend Correction Pipeline ADC Verilog-A Modeling

Abstract:

In this paper, a 12 bits pipeline ADC (analog to digital converter) based on digitally assisted backend correction is described and behaviorally modeled in Verilog-A language. The Verilog-A model is simulated with Cadence Spectre simulator. In the traditional use of pipeline ADC, the for-end sample and hold amplifier occupies the most power consumption. To decreases the system power consumption, open-loop amplifier is used in the first residual amplify circuit between first and second stage sub-ADC. To correct the nonlinear error introduced by the open-loop amplifier, backend digitally correction is applied.

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Periodical:

Advanced Materials Research (Volumes 457-458)

Pages:

1122-1128

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.457-458.1122

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Online since:

January 2012

Authors:

Yue Hong Gong, Min Luo, Jian Guo Ma

Keywords:

Backend Correction, Digitally Assisted, Open-Loop Amplifier, Pipeline ADC, Verilog-A

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References

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