A Study in Functional Verification of ASIP

Abstract:

ASIP can fulfill data processing effectively and flexibly in specific application. Due to the instruction’s diversity and the flexibility of logical structure, it has increased test vectors and enhanced difficulty in the functional verification of ASIP [1].With the continuous spread of ASIP application, the scale of designing is enlarging and the functional verification has become the bottleneck of designing of ASIP. This paper presents a methodology able to accomplish the functional verification of ASIP. The “Bottom-up” methodology is composed of the component-level verification, the instruction-level verification and the FPGA-based prototype system verification. The paper proves the feasibility and efficiency through the experiments in functional verification of ASIP.

• Periodical: Advanced Materials Research (Volumes 457-458)
• Pages: 218-224
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.457-458.218
• Online since: January 2012
• Authors: Jian Zhou Xu, Jin Hai Su, Zi Bin Dai, Wei Li
• Keywords: Application Specific Instruction-Set Processor (ASIP), Component-Level Verification, Coverage, Instruction-Level Verification, Prototype System Verification

References

[1] Jie Yu, Xi Li, Yan-yan Gao, Validation of ASIP Architecture Description, " Embedded Computing, 2008. SEC, 08. Fifth IEEE International Symposium on, pp.88-93.

DOI: 10.1109/sec.2008.49

[2] Zhongliang Pan, Simulation and verification of digitial circuits, Beijing: National Defense Industry Press, (2006).

[3] Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero, Evolutionary test program induction for microprocessor design verification, " Test Symposium, 2002. (ATS , 02). Proceedings of the 11th Asian, pp.368-373.

DOI: 10.1109/ats.2002.1181739

[4] Yang Guo, Wanxia Qu, Tun Li, Sikun Li, Coverage Driven Test Generation Framework for RTL Functional Verification, Computer-Aided Design and Computer Graphics, 2007 10th IEEE International Conference on. pp.32-326.

DOI: 10.1109/cadcg.2007.4407902

[5] M. Benjamin, D. Geist, A. Hartman, G. Mas, Y. Wolfsthal, R. Smeets, A Study in Cverage-Driven Test Generation, Design Automation Conference, 1999. Proceedings. 36th, pp.970-975.

DOI: 10.1145/309847.310108

[6] Haihua Shen, Lin Ma, Heng Zhang, CRPG: A configurable random test-program generator for microprocessor, " ISCAS, 05, Japan, 2005, vol. 4, pp.4171-4174.

DOI: 10.1109/iscas.2005.1465550

[7] Lin Yi-fan, Zeng xiao-yang, Wu Min, Chen Jun, Bao Ren-cheng, New Methods of FPGA Co-verification for System on Chip(SoC), ASICON 2005, 6th International Conference on ASIC, 2005, vol. 1, pp.219-222.

DOI: 10.1109/icasic.2005.1611289