FPGA Implementation of Real-Time Adaptive Bidirectional Equalization for Histogram

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According to the characteristics of infrared images, a contrast enhancement algorithm was presented. The principium of FPGA-based adaptive bidirectional plateau histogram equalization was given in this paper. The plateau value was obtained by finding local maximum and whole maximum in statistical histogram based on dimensional histogram statistic. Statistical histogram was modified by the plateau value and balanced in gray scale and gray spacing. Test data generated by single frame image, which was simulated by FPGA-based real-time adaptive bidirectional plateau histogram equalization. The simulation results indicates that the precept meet the requests well in both the image processing effects and processing speed

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215-219

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February 2012

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© 2012 Trans Tech Publications Ltd. All Rights Reserved

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[1] C. Bellotti, F. Bellotti, A. De Gloria, L. Andreone, M. Mariani. Developing a Near Infrared Based Night Vision System [J], IEEE Intelligent Vehicles Symposium, 686—691(2004).

DOI: 10.1109/ivs.2004.1336467

Google Scholar

[2] Takayuki Tsuji, Hiroshi Hattori, Masahito Watanabe, Nobuharu Nagaoka. Development of Night-Vision System [J], IEEE TRANSACTIONS ON INTELLIGENT TRANSPORTATION SYSTEMS, 3(3): 203—209(2002).

DOI: 10.1109/tits.2002.802927

Google Scholar

[3] Michael J. Potel. Night Vision: Infrared Takes to the Road [J], IEEE Computer Graphics and Applications, 6—10(1999).

Google Scholar

[4] Rita Kovordanyi, Torbjom Alm, Kjell Ohlsson. Night-Vision Display Unlit during Uneventful Periods May Improve Traffic Safety [J], IEEE Intelligent Vehicles Symposium, 282—287(2006).

DOI: 10.1109/ivs.2006.1689642

Google Scholar

[5] Digregorio, B.E. Safer driving in the dead of night-infrared vision systems[J], IEEE Spectrum, 43(3): 20—21(2006).

DOI: 10.1109/mspec.2006.1604835

Google Scholar

[6] Gavin L. Bates, Saeid Nooshabadi. FPGA Implementation of a Median Filter [J], IEEE TENCON-Speech and Image Technologies for Computing and Telecommunications, 2: 437—440(1997).

DOI: 10.1109/tencon.1997.648210

Google Scholar

[7] Maheshwari, R,. Rao, S.S.S. P,. Poonacha, P.G.: FPGA Implementation of Median Filter [J], IEEE Tenth International Conference on VLSI Design, 523—524(1997).

DOI: 10.1109/icvd.1997.568194

Google Scholar