An Implementation Method of Encrypting Partial Bitstream Based on FPGA

Wei Wang; Fei Xu; Jun Yin

doi:10.4028/www.scientific.net/AMR.479-481.2424

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 479-481An Implementation Method of Encrypting Partial...

An Implementation Method of Encrypting Partial Bitstream Based on FPGA

Abstract:

Partial reconfiguration of FPGAs requires loading partial bitstream. But loading a faulty or corrupted partial bitstream might cause some errors when undergoing reprogramming; what’s more, it may damage the FPGA device. A encrypt method based on cyclic redundancy check (CRC) before loading them into the device is introduced. The encrypt method of partial bitstream can realize the data integrity and security of FPGA Partial Reconfiguration.

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Periodical:

Advanced Materials Research (Volumes 479-481)

Pages:

2424-2428

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.479-481.2424

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Online since:

February 2012

Authors:

Wei Wang, Fei Xu, Jun Yin

Keywords:

AES, Encrypting Partial Bitstream, Field-Programmable Gate Array (FPGA), Partial Reconfiguration

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References

[1] Fengyan Wu. The dynamic partial reconfigurable system based on FPGA,In Chinese. Master's degree thesis,Guang Xi province: Guang Xi university,2010.

Google Scholar

[2] Wancai Li, Ying Wang, Jun Xu, Chenglian Peng.Design of data encryption in reconfigurable system, In Chinese.Computer Engineering and Design, 20rd ed,vol.29,2008,pp.5148-5149.

Google Scholar

[3] Zhenzhen Liu. Implementation of AES Encryption based on FPGA, In Chinese. Modern electronic technology, 23rd ed, 2007,pp:103-104.

Google Scholar

[4] Yun Tian, Wenbo Xu, Bin Hu. Xilinx ISE Design Suite 10.x Guide.Posts&Telecom Press,Bei jing,2008.

Google Scholar

[5] Xilinx,XAPP887(v1.0) PRC/EPRC:Data Integrity and Security Controller for PartialReconfiguration January 12, 2011.

Google Scholar

[6] Xilinx,UG191(V3.9.1), Virtex-5 FPGA Configuration User Guide,August,20,2010.http://www.xi-linx.com/support/documentation/user_guides/ug191.pdf

Google Scholar