A High Performance Hardware Architecture of Sub-Pixel Interpolator for H.264/AVC Encoder

Guang Hua Chen; Wen Peng Su; Feng Jiao Wang; An Qi Wang; Wei Min Zeng; Ren Jie Wang; Sun Fang Dai

doi:10.4028/www.scientific.net/AMR.479-481.2521

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 479-481A High Performance Hardware Architecture of...

A High Performance Hardware Architecture of Sub-Pixel Interpolator for H.264/AVC Encoder

Abstract:

The design of H.264/AVC interpolation unit is very challenging for the high memory bandwidth and large calculation complexity caused by the new coding features of variable block size (VBS) and 6-tap filter. In this paper, a novel one-step interpolation implementation algorithm is proposed which can effectively reduce processing cycle because of its less memory accessing. Moreover, a data reuse scheme is used to save processing cycle and memory bandwidth. A high performance hardware architecture is implemented according to the methods mentioned above. As a result, 26% memory bandwidth reduction and 45% processing cycle reduction are achieved, which shows that our architecture is an efficient hardware accelerating solution and can be used in real-time encoder.

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Periodical:

Advanced Materials Research (Volumes 479-481)

Pages:

2521-2524

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.479-481.2521

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Online since:

February 2012

Authors:

Guang Hua Chen, Wen Peng Su, Feng Jiao Wang, An Qi Wang, Wei Min Zeng, Ren Jie Wang, Sun Fang Dai

Keywords:

Data Reuse, H.264/AVC, One-Step Interpolation

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References

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