A Low-Power ΣΔ Modulator Using Asynchronous SAR Quantizer for Sensor Application

Wei Lang; Pei Yuan Wan; Ping Fen Lin

doi:10.4028/www.scientific.net/AMR.482-484.241

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 482-484A Low-Power ΣΔ Modulator Using Asynchronous SAR...

A Low-Power ΣΔ Modulator Using Asynchronous SAR Quantizer for Sensor Application

Abstract:

This paper presents a low power ΣΔ modulator for a low power microsensor application. The ΣΔ modulator adopts second-order single loop topology with input feed-forward path. An asynchronous 4-bit successive approximation (SAR) quanztizer is employed to digitize the analog input. Inherent summation of SAR quantizer is utilized as analog summation. The switched operational amplifier is used in first integrator to reduced power consumption. The modulator, simulated at the transistor level using 0.13-μm CMOS technology, obtains a peak SNDR of 93 dB over an input signal of 5 kHz and simulation power consumption is 340 μW from 1-V supply.

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Periodical:

Advanced Materials Research (Volumes 482-484)

Pages:

241-244

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.482-484.241

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Online since:

February 2012

Authors:

Wei Lang, Pei Yuan Wan, Ping Fen Lin

Keywords:

Asynchronous, Low Power, Successive Approximation, ΣΔ

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