Simple Transmission Performance Analysis System of Digital Signal Using FPGA

Xiao Zhang; Jie Song; Hao Ding

doi:10.4028/www.scientific.net/AMR.588-589.794

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 588-589Simple Transmission Performance Analysis System of...

Simple Transmission Performance Analysis System of Digital Signal Using FPGA

Abstract:

This article has designed a digital signal transmission performance analysis system using FPGA. It uses FPGA to generate the m-sequence whose frequency can be adjusted step by step and it uses Manchester encoding. Through the transmission channel, a fast bit synchronization detection arithmetic is used to abstract bit synchronization clock by FPGA. The oscilloscope can use the bit synchronization clock to observe eye diagram and other information. The system has the advantages of good transplant, small size, low-power consumption and high reliability.

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Periodical:

Advanced Materials Research (Volumes 588-589)

Pages:

794-797

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.588-589.794

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Online since:

November 2012

Authors:

Xiao Zhang, Jie Song, Hao Ding

Keywords:

Bit Synchronization, Field-Programmable Gate Array (FPGA), Manchester Encoding, M-Sequence

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References

[1] Sun Jinsheng, Shi Baoyou, Design and Implementation of Modbus Remote I/O based on CPLD, Manufacturing Automation, vol. 30, no. 7, 2008, pp.47-54.

Google Scholar

[2] T. Fogarty, J. Miller, and P. Thompson, Evolving digital logic circuits on Xilinx 6000 family FPGAs, in Soft Computing in Engineering Design and Manufacturing, P. Chawdhry, R. Roy, and R. Pant (eds. ), Springer: Berlin, 2008, p.299–305.

DOI: 10.1007/978-1-4471-0427-8_32

Google Scholar

[3] T. Fogarty, J. Miller, and P. Thompson, Evolving digital logic circuits on Xilinx 6000 family FPGAs, in Soft Computing in Engineering Design and Manufacturing, P. Chawdhry, R. Roy, and R. Pant (eds. ), Springer: Berlin, 2008, p.299–305.

DOI: 10.1007/978-1-4471-0427-8_32

Google Scholar

[4] P. Graham and B. Nelson, Genetic algorithms in software and in hardware—A performance analysis of workstation and custom computing machine implementations, in Proc. Fourth IEEE Symp. FPGAs for Custom Comput. Mach., K. Pocek and J. Arnold (eds. ), IEEE Computer Society Press: Napa Valey, CA, Apr., 2006, p.216.

DOI: 10.1109/fpga.1996.564847

Google Scholar

[5] Sergey Primak. On the generation of correlated time series with a given probability density function[J]. Signal Processing, 1999, pp.213-216.

DOI: 10.1016/s0165-1684(98)00165-0

Google Scholar

[6] He Wenlong, Fang Jiandong, Control Method for Digital Temperature Sensor based on FPGA, Electronic Measurement Technology, vol. 31, no. 11, 2008, pp.178-181.

Google Scholar