Full-Custom Design and Implementation of High-Performance Multiplier

Abstract:

I proposed a method of using full-custom design 32 × 32 multiplier to enhance performance, reduce the power consumption and the area of layout. I use improved Wallace tree structure for partial product compression, truncated beyond the 64 part of the plot and the look-ahead logarithmic adder using Radix-4 Kogge-Stone tree algorithm raise the multiplier performance. In the design of Booth2 encoding circuit and compression circuit, I use a transmission gate logic design with higher speed and smaller area. I also use Euler path method and heuristic Euler path method to reduce the layout area. The design use SMIC 0.18μm 1P4M CMOS process, with a layout area of 0.1684mm2. In a large number of test patterns, simulation results show that the computation time of a 32 × 32 multiplication is less than 3.107ns.

• Periodical: Advanced Materials Research (Volumes 631-632)
• Pages: 1445-1451
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.631-632.1445
• Online since: January 2013
• Authors: Ren Ping Wang
• Keywords: Heuristic-Euler Path Method, Improved Wallace Tree, Partial-Product Compressor, Radix-4 Kogge-Stone Tree, Transmission Gate Logic

References

[1] T.V. More, and Dr.R.V. Kshirsagar, Design of Low Power Column Bypass Multiplier using FPGA, IEEE journal of solid-state circuits, vol. 31, pp.1535-1546, (2011).

DOI: 10.1109/icectech.2011.5941786

[2] K. Shiannrong, and W. Jiunping, Design of Power-Efficient Configurable Booth Multiplier, IEEE transactions on circuits and systems regular papers, vol. 57, no. 3, pp.568-580, (2010).

DOI: 10.1109/tcsi.2009.2023763

[3] S. Kuang, W. Jiunping, and G. Cangyuan, Modified Booth Multipliers with a regular partial product array, IEEE Trans on Circuits and Systems, vol. 56, no. 5, pp.404-408, (2009).

DOI: 10.1109/tcsii.2009.2019334

[4] L. Junqiang, L. Dongsheng and L. Yilei, 32×32 High-speed Multiplier Design and Implementation, MICROELECTRONICS & COMPUTER, vol. 26, no. 12, pp.22-26, (2009).

[5] Huang Y M, and James B K, A high-speed conditional carry select(CCS) adder circuit with a successively incremented carry number block structure for low-voltage VLSI implementation, IEEE Transaction on Circuits and Systems, vol. 47, no. 10, pp.1074-1079, (2000).

DOI: 10.1109/82.877148

[6] Y. Wenchang, and J. Cheinwei, High-speed booth encoded parallel multiplier design, IEEE Transaction on Computers, vol. 49, no. 7, pp.692-701, (2000).

DOI: 10.1109/12.863039

[7] J. Rabeay, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuit: A Design Perspective, second ed., Prentice-Hall, Upper Saddle River, NJ, (2003).

[8] W. Renping, H. Minghua, and W. Rongshan, Full-custom design of high-performance 64-bit Parall-Prefix adder, Journal of Fuzhou University (Natural Science Edition), vol. 39, no. 6, pp.862-867, (2011).

[9] D.A. Hodges, H.G. Jackson, R.A. Saleh, Analysis Design of Digital Integrated Circuits-In Deep Submicron Technology, third ed., McGraw-Hill, New York, (2004).