Evaluation of ESD/LU Reliabilities by Different SCR Layout Types in a 0.35μm 3.3V CMOS Process

Shen Li Chen; Chun Ju Lin

doi:10.4028/www.scientific.net/AMR.779-780.1124

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 779-780Evaluation of ESD/LU Reliabilities by Different...

Evaluation of ESD/LU Reliabilities by Different SCR Layout Types in a 0.35μm 3.3V CMOS Process

Abstract:

This paper aimed at the evaluation of layout dependence on ESD/LU reliabilities in the 0.35μm 3.3V low-voltage triggered silicon-controlled-rectifier (LVTSCR) DUTs. In this work, the parameter of channel L in a pMOS and the parameter S of an SCR are varied to study the influence on trigger voltage (V_t1), holding voltage (V_h) and secondary breakdown current (I_t2), respectively. Eventually, it can be found that the layout illustration of type-2 has a higher I_t2 than that of type-1, i.e., the ratio of (I_t2)_type-2/(I_t2)_type-1> 3 among all the LVTpSCRs. Meanwhile, the holding voltage of all SCR devices are latch-up free while operated at 3.3V. Therefore, the type-2 layouts of SCR devices are so excellent structure in the ESD/LU reliability considerations for this 0.35μm 3.3V CMOS process.

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Periodical:

Advanced Materials Research (Volumes 779-780)

Pages:

1124-1129

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.779-780.1124

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Online since:

September 2013

Authors:

Shen Li Chen, Chun Ju Lin

Keywords:

Electrostatic Discharge (ESD), Holding Voltage (V_h), Latch-Up Effect (LU Effect), Low-Voltage Trigger Silicon-Controlled Rectifier (LVTSCR), Secondary Breakdown Current (I_t2), Snapback, Transmission-Line Pulse (TLP), Trigger Voltage (V_t1)

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References

[1] Ajith Amerasekera, Charvaka Duvvury: ESD in Silicon Integrated Circuits, 2nd ed., John Wiley & Sons Ltd, USA (2003).

Google Scholar

[2] Juin J. Liou: 28th International Conference on Microelectronics (MIEL 2012), p.11.

Google Scholar

[3] Zhiwei Liu, Juin J. Liou, Shurong Dong, and Yan Han: IEEE Electron Device Letters, Vol. 31, no. 8 (2010), p.845.

DOI: 10.1109/led.2010.2050575

Google Scholar

[4] M. J. Hargrove, S. Voldman, R. Gauthier, J. Brown, K. Duncan, and W. Craig: Proc. of IEEE Int. Reliability Physics Symp. (1998), p.269.

Google Scholar

[5] Ming-Dong Ker, Kuo-Chun Hsu: IEEE Journal of Solid-State Circuits, Vol. 38, Issue: 8 (2003), p.1380.

DOI: 10.1109/jssc.2003.814434

Google Scholar

[6] Chen-Shang Lai, Meng-Hwang Liu, Shin Su, and Tao-Cheng Lu: 2003 International Symposium on VLSI Technology, Systems, and Applications (2003), p.80.

DOI: 10.1109/vtsa.2003.1252557

Google Scholar

[7] Chih-Yao Huang, Quo-Ker Chen, Ming-Fang Lai, Fu-Chien C. Chiu, Jen-Chou C. Tseng: 16th IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (2009), p.363.

DOI: 10.1109/ipfa.2013.6599129

Google Scholar

[8] Shurong Dong, Hao Jin, Meng Miao, Jian Wu, and Juin J. Liou: IEEE Electron Device Letters, Vol. 33 , no. 5 (2012), p.640.

Google Scholar

[9] Guang Chen, Le Gao, Ning Zhang, Shaolong Liu, Yu-Hua Cheng: 3rd International Conference on Computer Research and Development (ICCRD 2011), p.402.

DOI: 10.1109/iccrd.2011.5764224

Google Scholar

[10] Qiang Cui, Shurong Dong, Yan Han: IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC 2012), p.1.

DOI: 10.1109/edssc.2012.6482791

Google Scholar

[11] Rahul, Mishra, Junjun Li, Di Sarro, James P., John Campi, Robert J. Gauthier: 34th Electrical Overstress/Electrostatic Discharge Symposium (2012), p.1.

Google Scholar