A FPGA-Based Design of Floating-Point FFT Processor with Dual-Core

Jun Ding; Na Li

doi:10.4028/www.scientific.net/AMR.811.441

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 811A FPGA-Based Design of Floating-Point FFT...

A FPGA-Based Design of Floating-Point FFT Processor with Dual-Core

Abstract:

This paper presents a dual-core floating point FFT processor design based on CORDIC algorithm, enabling high-speed floating-point real-time FFT computation, and its time complexity is (N / 4) Log (N / 2). The design unifiesthe floating complex multiplication and the evaluationof twiddle factors into an iteration, which not only reduces the complexity of complex multiplication but also reduces the difficulty when the butterfly unit deals with floating-point in fast Fourier transform. The butterfly unit unaffected by the size of external memory can handle the Fourier transform with high sample number, both having wider handling range and high handling precision. It uses two logical cores and pipeline technology to improve overall system throughput, with simple hardware structure and system stability.At the end, it does the post-simulation on the Altera chip EP2C35F672C6, and its timing simulation can be run properly under the 50 MHz clock frequency.

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Periodical:

Advanced Materials Research (Volume 811)

Pages:

441-446

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.811.441

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Online since:

September 2013

Authors:

Jun Ding, Na Li

Keywords:

CORDIC Algorithm, Dual-Core, FFT, Field-Programmable Gate Array (FPGA), Floating Butterfly Operation

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