Research on Synchronous Parallel Coding Algorithm of Medium Length BCH and FPGA Implementation

Ce Lun Liu; Kai Zhang; Sen Quan  Fan; Yan Dong Huang

doi:10.4028/www.scientific.net/AMR.846-847.1084

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Research on Synchronous Parallel Coding Algorithm of Medium Length BCH and FPGA Implementation
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Research on Synchronous Parallel Coding Algorithm of Medium Length BCH and FPGA Implementation

Abstract:

The error correction capability of BCH is very strong, especially for the short and medium length of codes, which performance reaches the theory value. Besides, it has a strict algebraic structure, which plays an important role in the encode theory. But traditional serial BCH has a low throughput, so it cannot satisfy high speed communication. This paper designed a parallel synchronization encode and decode algorithm, and used FPGA to simulate. Experiment result shows that the proposed algorithm can satisfy the requirement of code rate and hardware resources consumption, so the algorithm has a very useful practical value.