Parallel Implementation of High Speed Mono-Pulse Angle Estimation Processor Based on Multi-IC Architecture

Yan Xian Bi; Yu Xi Zhang; Chang Shun Yuan; Yu Xian Zhang

doi:10.4028/www.scientific.net/AMR.846-847.1225

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 846-847Parallel Implementation of High Speed Mono-Pulse...

Parallel Implementation of High Speed Mono-Pulse Angle Estimation Processor Based on Multi-IC Architecture

Abstract:

This paper proposes a kind of high speed mono-pulse sum-difference angle estimation hardware architecture. Sum-difference amplitude mono-pulse algorithm is implemented in the hardware which is composed of 4 chips of XC6VSX315T and three chips of TMS320C6678. This hardware structure has already been applied in engineering.

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Periodical:

Advanced Materials Research (Volumes 846-847)

Pages:

1225-1229

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.846-847.1225

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Online since:

November 2013

Authors:

Yan Xian Bi*, Yu Xi Zhang, Chang Shun Yuan, Yu Xian Zhang

Keywords:

FPGA+DSP, Mono-Pulse, Parallel Architecture, Sum-Difference Amplitude

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