Four Bit Priority Resolution Network Using Current Mode Winner Take all Circuit

Abstract:

This paper presents a new approach for making a four bit priority resolution circuit using current mode winner Take all (WTA) analog computation cells, the winner-takes-all circuit is employed to evaluate the highest input among a set of competing inputs and inhibit the others. This circuit consists of an input stage, a current mode Lazzaros WTA circuit and an output stage consisting of current mirror and load resistor. This circuit is compact, consisting of a total of 28 transistors including the input stage, and a good linearity is observed in response. Simulation of proposed circuit is performed on cadence virtuoso software in 0.18 μm CMOS process technology.

• Periodical: Advanced Materials Research (Volumes 889-890)
• Pages: 886-889
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.889-890.886
• Online since: February 2014
• Authors: Wen Qin Cao*, Hai Yan Zhu, Guo Ping Tu
• Keywords: Current Mode WTA Circuit, Prescaling Input Stage, Priority Encoder, Priority Resolution Network

References

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