ESD Failure Analysis and Robustness Design in Vertical-Diffused MOS Transistors

Abstract:

This paper deals with a detailed study of ESD failure mode and how to strengthen of the VDMOS used for power applications. The ESD post-zapped failure of power VDMOS transistors due to HBM, MM, and CDM stresses are examined in this work. Through standard failure analysis techniques by using EMMI and SEM were applied to identify the failure locations. The MM failure mode in this power MOSFET was caused by the gate oxide breakdown near n⁺ region in the source end as an ESD zapping. And, the ESD failure damage under HBM and CDM stresses were caused by the gate material molten near the gate pad and tunneled through the oxide layer into silicon epitaxial layer. Furthermore, the ESD robustness designs of power VDMOS transistors are also addressed in this work. The first ESD incorporated design is Zener diodes back-to-back clamping the gate-to-source pad, and on the other hand, another one excellent design contains two Zener diodes clamping the gate-to-source and gate-to-drain terminals of a VDMOS, respectively.

• Periodical: Advanced Materials Research (Volumes 926-930)
• Pages: 456-461
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.926-930.456
• Online since: May 2014
• Authors: Shen Li Chen*, Wen Ming Lee, Chi Ling Chu
• Keywords: Charged-Device Model (CDM), Electrostatic Discharge (ESD), Emission Microscope (EMMI), Fowler-Nordhein (FN) Tunneling, Human-Body Model (HBM), Machine Model (MM), Vertical-Diffused MOS (VDMOS)

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