Design and Realization of Efficient Verification Platform Based on System Verilog

Abstract:

Adopting the Verification Methodology Manual’s (VMM) hierarchical structure, this paper presents a design of available verification platform based on System Verilog adopted. The platform completed can implement constrained-random test, directed test, and error stimulus test with high efficiency; moreover, gain maximum code reuse. Using Direct Programming Interface (DPI), the verification platform can conveniently link C++ with the model that realized the function of Design Under Test (DUT), and then to test it. At last the paper shows the experiment results to prove the effectiveness and practicality of the platform by verification sample of HOG chip.

• Periodical: Advanced Materials Research (Volumes 945-949)
• Pages: 1903-1907
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.945-949.1903
• Online since: June 2014
• Authors: Mei Hua Xu, Qin Yu, Ai Ying Guo
• Keywords: HOG, System Verilog, Verification, VMM

References

[1] Bergeron, Janick: Writing Testbenches Using SystemVerilog, Norwell, MA: Springer (2006).

[2] Q. Zhu, M. Yeh, K. Cheng, and S. Avidan: Fast Human Detection Using a Cascade of Histograms of Oriented Gradients, Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition (2006).

DOI: 10.1109/cvpr.2006.119

[3] Cummings, Cliff, Salz, Arturo: SystemVerilog Event Regions, Race Avoidance & Guidelines, Synopsys User Group, Boston, CA (2006).

[4] Sutherland, Stuart, Davidmann, Simon, Flake, Peter, and Moorby, Phil: System-Verilog for Design: A Guide to Using System Verilog for Hardware Design and Modeling, Norwell, MA: Springer (2006).

[5] Keaveney, Martin, McMahon, Anthony and O'Keeffe, Niall: The development of advanced verificationenvironments using System Verilog, Signals and Systems Conference (2008), pp.325-330.