Design of Parallel Prefix Adder

Abstract:

The fundamental algorithms of many additional applications, including those that deal with machine learning, signal processing, image processing, and video processing, depend heavily on addition units. In addition to their intrinsic value, addenda are essential for many mathematical operations such as division, multiplication, squaring, and comparison. The parallel prefix adder (PPA) is among the fastest adders available. The efficient parallelization implementation of Parallel Prefix Adders (PPAs) in the carry production (G) and propagation (P) phases may be responsible for their fast performance. A PPA approximation based on estimates from POs is presented in this work. Each of these requires less energy than the others. Keywords—Adder, Signal processing, Algorithm, Parallel Prefix Adder,

• Periodical: Engineering Headway (Volume 16)
• Pages: 49-56
• DOI: https://doi.org/10.4028/p-N2Vc6o
• Online since: January 2025
• Authors: T. Mani*, M. Kathirvelu, A. Harishkumar, S. Praveen, N. Selvakumar, M. Dhanushiya
• Keywords: Adder, Algorithm, Parallel Prefix Adder, Signal Processing

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