Key Engineering Materials Vol. 643

Abstract: This paper presents usage of analog feed-forward control to improve the transient response of DC-DC buck converters with pulse-width-modulation (PWM). The analog feed-forward controller is simple and does not require complicated calculations. Duty cycle is modulated directly based on the charge balance of the output capacitor. Compared with conventional feedback control, this simple feed-forward controller reduces control delay and provides a satisfactory transient response. We apply this technique to a Single-Inductor-Dual-Output (SIDO) buck converter as well as a Single-Inductor-Single-Output (SISO) buck converter, and show that its cross-regulation is improved. We have validated the proposed method with SIMetrix simulations.

Abstract: This Paper Describes Application of the Hysteresis Control to the Single-Inductordual-Output (SIDO) Power Supply Circuit to Realize High Performance, Low Cost and Small Sizepower Supply Circuits. the Sidos can Realize Small Number of Inductors (hence Small Size Andlow Cost) in the System where Multiple Power Supplies are Required, but their Performance Isnot Very Good if Conventional SIDO Control Methods are Used. we Show with Simulation Andexperiment that the Hysteresis Control can Realize High Performance SIDO Converters.

Abstract: This paper proposes an innovative method of converting digital signal to time-domain analog signal, which fully enjoys robustness and digital circuit friendliness. This technique utilizes a digital delta-sigma ( ) modulator following a digital-to-time converter (DTC) circuit with various modulation methods. As an application of the proposed method, novel spreadspectrum clock generation (SSCG) algorithms (such as for DC-DC converters) have been investigated which can select the noise spectrum spread bands; e.g., they can exclude the noisespectrum spread in AM, FM radio bands. The proposed circuit takes advantage of digital technology, which is simple, fast (reachable at high clock frequency) and flexible (programmable).

Abstract: This paper presents an ADC architecture comprising a pipelined cyclic ADC and continuous-time delta-sigma ADC; it provides high resolution at medium speed, with small power requirements. It is also reconfigurable for different combinations of speed, precision, and power consumption. The cyclic ADC produces a residue after the final cycle, and the following delta-sigma ADC converts it to a digital value (the residue is then noise-shaped). The ADC output combines the digital outputs of the cyclic ADC and the delta-sigma ADC so as to achieve high resolution. The delta-sigma ADC can be implemented simply with continuous-time analog circuitry. We describe the overall ADC architecture and operation, show simulation results, as well as features such as its potential for reconfiguration and one of ADC architecture candidates with good tradeoff for high resolution, medium speed and small power.

Abstract: This paper presents algorithms for improving spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) — targeted at communication applications — by minimizing both current-source mismatches and glitches. Conventional segmented current-steering DACs suffer from static mismatches among current sources which cause nonlinearity and degrade SFDR, though glitch energy is relatively small. The data-weighted averaging (DWA) algorithm can reduce static current source mismatch effects, but it increases the effects of glitch energy. Here we investigate the use of both conventional Switching-Sequence Post-Adjustment (SSPA) calibration and One–Element-Shifting (OES) methods in order to reduce the effects of both nonlinearity and glitch energy. For further improvement, we propose and investigate a fully-digital combined algorithm to reduce static current source mismatch effects with minimal increase in the glitch energy. We also did simulations of the effect of combining these two compensation methods. Our MATLAB simulations show that the combined algorithm can improve SFDR performance by 24 dB, 22dB and 2dB compared to conventional thermometer-coded, one-element-shifting and SSPA methods respectively in some conditions. When we take current mismatch into account, the combined algorithm causes glitch energy to increase by only 0.02 to 0.2 % compared to the other three methods alone.

Abstract: This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing the input signal of the noise cancellation amplifier, the nonlinear effect on the amplifier can be reduced, as well as the power consumption can be smaller. Furthermore, as a lower gain of the noise-canceling sub-amplifier can be achieved simultaneously, further reduction of the power consumption becomes possible. The verification of the proposed technique is conducted with Spectre simulation using 90nm CMOS process.

Abstract: The purpose of this research is to characterize and model the self-heating effect of n-channel Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistors (LDMOS). In order to improve the accuracy and convergence of the self-heating (SH) simulations in DC, transient and small signal AC (S-Parameter) domains, a new SH model has been developed and implemented in Verilog-A version of BSIM4 model to simulate an LDMOS device. The new SH model does not require a separate thermal network. It has been verified with measurements in static DC, transient, and small signal AC (S-parameter). Excellent agreements between measured and simulated results have been obtained without sacrificing simulation speed and convergence performance.

Abstract: This paper describes digital auto-tuning schemes for second-order Gm-C bandpass filters which are suitable for fine CMOS implementation. We propose a switched Gm-C analog filter and two digital tuning schemes: a center frequency tuning scheme using the phase information and a Q factor tuning scheme using the magnitude information. We present circuits, describe their operations, and present SPICE simulation results.

Abstract: This Paper Describes our Challenge of Automatic Analog Circuit Design by Focusingon a Comparator Circuit which is One of the Important Analog Building Blocks. the Geneticalgorithm Chooses the Optimal Circuit Topology and HSPICE Optimizing Function Obtains Theiroptimal Parameter Values Automatically. Automatic Design for Analog Circuit has Not Beenrealized yet, even though Automatic Design is being Used in Digital Circuit Design; the Reasonbehind this is that the Number of Parameters to Be Considered in an Analog Circuit Designis much Larger than Digital Circuit Design. Nowadays it is Extremely Difficult to Design Icsmanually due to their Large Scale Integration and Hence their Automatic Design is Demanded. Wepresent our Automatic Circuit Design Owchart Programmed with Java Language which Realizes1-Click Automatic Synthesis of the Comparator, and Shows that our Method can Obtain a Betterperformance Comparator Compared to an Initially-Set Comparator.

Abstract: As the Required Data Rate for VLSI System Communication Increases, Channel Bandwidthlimitation Becomes a Crucial Problem as High-Frequency Channel Loss Degrades the Transmission Performance.In this Paper, we Compare Non-Return-to-Zero (NRZ) Binary and 4-PAM (pulse Amplitudemodulation) Coding Techniques for High-Speed Data Transmission by Fabricating a Test Board of a Microstripline. by Extracting the Micro-Strip Line Parameters, we Carry out Co-Simulations to Evaluate Spectrallyefficient Coding for High-Speed Data Transmission.We Consider the Conditions for which 4-Pamsignaling Provides an Advantage over NRZ Signaling from the Viewpoint of Channel Profiles.