Papers by Author: Anthony G. O'Neill

Abstract: We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (D_IT) at the SiC/SiO₂ interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm²·V^-1·s^-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the D_IT and channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

Abstract: This work presents experimental evidence of the formation mechanisms of few-layer graphene (FLG) films on SiC by nickel silicidation. FLG is formed by annealing of a 40 nm thick Ni layer on 6H-SiC at 1035^ºC for 60 s, resulting in a Ni₂Si layer which may be capped by any Ni that did not react during annealing. It has been proposed that FLG forms on top of the Ni during the high temperature stage. In contrast, during cooling, carbon atoms which were released during the silicidation reaction may diffuse back towards the Ni₂Si/SiC interface to form a second FLG film. After annealing, layer-by-layer de-processing was carried out in order to unequivocally identify the FLG at each location using Atomic force microscopy (AFM) and Raman spectroscopy.

Abstract: Multilayer epitaxial graphene has been grown on the Si-face of 6H-SiC on-axis commercial substrates under high vacuum conditions and at growth temperatures up to 1900 °C, utilizing the standard sublimation growth technique and a modified SiC rapid thermal annealing system which allows for excellent control of heating and cooling ramp rates. The peak growth temperature and total growth time during the graphene growth step, along with the temperature of the initial substrate etch step, were all systematically varied in order to ascertain their effect on the formation of epitaxial graphene films on the SiC surface. Modifying the substrate etch temperature was found to have a significant impact on the morphology of the SiC substrate, with a uniform step structure only developing across the surface within a narrow temperature band. Furthermore, changing the values of the peak temperature or the growth time during the growth step were both shown to have a large effect on the resultant materials properties of the graphene films.

Abstract: Patterned Few Layers Graphene (FLG) films were grown by local solid phase epitaxy from nickel silicide supersaturated with carbon. The process was realised by annealing of thin Ni films deposited on the carbon-terminated surface of 6H-SiC semi-insulating wafer followed by wet processing to remove the resulting nickel silicide. Raman spectroscopy was used to investigate both the formation and subsequent removal of nickel silicide during processing. Characterisation of the resulting FLG films was carried out by Raman spectroscopy and Atomic Force Microscopy (AFM). The thickness of the final FLG film estimated from the Raman spectra varied from 1 to 3 monolayers for initial Ni layers varying from 3 to 20 nm thick. AFM observations revealed process-induced surface roughening in FLG films, however, electrical conductivity measurements by Transmission Line Model (TLM) structures confirmed that roughness does not compromise the film sheet resistance.

Abstract: Buried gate static induction transistors (BGSITs) were fabricated on commercial 4H-SiC wafer with 20 m thick n-type epilayer having a net donor density of 0.71015 cm-3. Buried gate regions were formed by the selective implantation of high energy (up to 2 MeV) aluminium performed at 600 °C. Nitrogen was implanted at temperature of 400 °C to form a heavily doped blanket source region. Post-implantation annealing was carried out at the atmospheric pressure in argon using a graphite capping layer. Fabricated normally-on devices with source contact diameter of 0.2 mm were tested at temperatures up to 500 °C and current densities up to 270 A/cm2. The specific on-resistance of a completely open 4H-SiC BGSIT was 34 mcm2 and showed a thermally activated behaviour at temperatures up to 500 °C.

Abstract: Nickel silicide Schottky contacts were formed on 4H-SiC by consecutive deposition of a titanium adhesion layer, 4 nm thick, and nickel, 100 nm thick, followed by annealing at temperatures from 600 to 750 °C. It was found that contacts with barrier heights of 1.45 eV, consisting mainly of NiSi phase, formed in the 600-660 °C temperature range, while annealing at around 750 °C led to the formation of Ni2Si phase with barrier heights of 1.1 eV. Annealing at intermediate temperatures resulted in the nucleation of Ni2Si grains embedded in the NiSi film which were directly observed by micro-Raman mapping. It was concluded that the thermodynamically unfavourable NiSi phase appeared in the 600-660 °C temperature range due to the fact that the solid state chemical reaction between Ni and SiC at these temperatures is controlled by nickel diffusion through the titanium barrier.

Abstract: High voltage 4H-SiC Schottky diodes with single-zone junction termination extension (JTE) have been fabricated and characterised. Commercial 4H-SiC epitaxial wafers with 10, 20 and 45 +m thick n layers (with donor concentrations of 3×1015, 8×1014 and 8×1014 cm-3, respectively) were used. Boron implants annealed under argon flow at 1500°C for 30 minutes, without any additional protection of the SiC surface, were used to form JTE’s. After annealing, the total charge in the JTE was tuned by reactive ion etching. Diodes with molybdenum Schottky contacts exhibited maximum reverse voltages of 1.45, 3.3 and 6.7 kV, representing more than 80% of the ideal avalanche breakdown voltages and corresponding to a maximum parallel-plane electric field of 1.8 MV/cm. Diodes with a contact size of 1×1 mm were formed on 10 +m thick layers (production grade) using the same device processing. Characterisation of the diodes across a quarter of a 2-inch wafer gave an average value of 1.21 eV for barrier heights and 1.18 for ideality factors. The diodes exhibited blocking voltages (defined as the maximum voltage at which reverse current does not exceed 0.1 mA) higher than 1 kV with a yield of 21 %.

Abstract: 4H-SiC diodes with nickel silicide (Ni2Si) and molybdenum (Mo) Schottky contacts have been fabricated and characterised at temperature up to 400°C. Room temperature boron implantation has been used to form a single zone junction termination extension. Both Ni2Si and Mo diodes revealed unchanging ideality factors and barrier heights (1.45 and 1.3 eV, respectively) at temperatures up to 400°C. Soft recoverable breakdowns were observed both in Ni2Si and Mo Schottky diodes at voltages above 1450 V and 3400 V depending on the epitaxial structure used. These values are about 76% and 94% of the ideal avalanche breakdown voltages. The Ni2Si diodes revealed positive temperature coefficients of breakdown voltage at temperature up to 240°C.

Abstract: Physics-based analytical models are seen as an efficient way of predicting the characteristics of power devices since they can achieve high computational efficiency and may be easily calibrated using parameters obtained from experimental data. This paper presents an analytical model for a 4H-SiC Enhancement Mode Vertical JFET (VJFET), based on the physics of this device. The on-state and blocking behaviour of VJFETs with finger widths ranging from 1.6+m to 2.2+m are studied and compared with the results of finite element simulations. It is shown that the analytical model is capable of accurately predicting both the on-state and blocking characteristics from a single set of parameters, underlining its utility as a device design and circuit analysis tool.

Abstract: The evaluation of stress in sub-micron tracks is critical for the microelectronics industry and there is a need for new methods of measurement. This paper advocates the use of a rotating beam sensor structure which can be fabricated on the wafer along side electronic devices and used to monitor stress generation and relaxation as a function of processing. The rotation can be observed with a reflected light microscope and correlated to the actual stress level. Several samples, assputtered and sintered, were prepared with the aim of having different residual stress states. X-ray diffraction with a low incident angle geometry, was used to evaluate the residual stresses on the aluminum layer. Computer simulations using ANSYS were also performed in order to correlate the sensor rotation with the experimental stress values. It was observed that the extrinsic stress from the mismatch in expansion coefficients between the aluminum layer and the silicon substrate dominates over the compressive stress from the sputter growth. Sintering the layers at temperatures above 150°C reduces this compressive stress due to the action of creep. The calibration of the rotation of the device with the direct measurements of the X-ray diffraction shows that the sensor has a resolution better than 2.8 MPa.