Papers by Author: Francesco Moscatelli

Abstract: This study shows that an Al-Ti bilayer with an Al to Ti atomic ratio suitable forohmic contacts on p-type 4H-SiC can be covered by a Ni film during the high temperature alloying process, without altering the ohmic nature, while eliminating a detrimental contact morphology caused by the presence of molten Al-Si during alloying. On 1×10²⁰ cm^-3 Al-implanted 4H-SiC layer, the RT specific contact resistance of this Ni-Al-Ti contact measured by TLM-C method is (3 ± 1)×10^-6 Ωcm².

Abstract: Square shaped annular lateral p⁺–i–n⁺ diodes on high purity semi-insulating (HPSI) 4H-SiC are fabricated by Al⁺ and P⁺ ion implantation to obtain anode and cathode regions, respectively. All the diodes have the same size central anode surrounded by an intrinsic region, which is surrounded by an annular cathode. Anode area and annular cathode width are fixed for all diodes, only the lateral length of the intrinsic region is varied. Post implantation annealing is performed at 1950 °C for 10 min. Static forward and reverse characteristics are measured in the temperature range of 30 - 290 °C. For all diodes, the reverse current is below the instrument detection limit of 10^-14 A up to 100 °C at 200 V, the maximum reverse bias employed in this study. The reverse current increased up to low 10⁸ A for 200 V reverse bias at 290 °C. Forward currents overlap at the low voltage region once they exceed the instrument detection limit at ~1.6 V and 30 °C. The forward currents follow almost identical exponential trend at all measured temperatures while the diode series resistance increase with increasing anode-cathode distance and decreased with increasing temperature for the given intrinsic region lateral length.

Abstract: Two families of Al⁺ implanted vertical p⁺in diodes that have been processed all by identical steps except the post implantation annealing one have been characterized with current voltage measurements from -100 to +5V at different temperatures. Analysis of the static forward current voltage characteristics shows two different ideality factor regions, which are distinct for each family. The reverse current voltage characteristics reveals corresponding two different activation energies. These are assumed to be correlated to the Z_1/2 defect for the one case and another one with an activation energy of 0.25eV.

Abstract: We have investigated 3C-SiC layers grown on silicon and on poli-Si in order to realize test MEMS structures. The strain of the films were investigated by the fabrication of cantilevers, beams, springs and we successfully fabricated a Double-Ended-Tuning-Fork double clamped SiC resonator on the film, with perfectly aligned actuation electrode.

Abstract: In this study a pyrolyzed photoresist film that has been used for protecting the implanted surface of a 4H-SiC wafer during post implantation annealing at 1800-1950 °C has preserved on the wafer surface and used for the fabrication of ohmic contact pads on P+ implanted areas. The carbon film has been patterned by using a RIE O2-based plasma. A specific contact resistance of 9  10 5 cm2 has been obtained on P+ 1  1020 cm 3 implanted 4H-SiC. Micro-Raman characterizations show that the carbon cap is formed of a nano-crystalline graphitic phase.

Abstract: Comparative studies of gate oxides on a N+ pre-implanted area (Ninterface ~1x1019cm-3) and on a virgin Si face 4H-SiC material (Ninterface ~1x1016cm-3) have been undertaken by means of Capacitance-Voltage (C-V) characteristics, performed at different temperatures and frequencies, and Thermal Dielectric Relaxation Current technique. In the non implanted samples, the stretch out of the C-V curves get larger as the temperature is lowered to 150K, while for lower temperatures the C-V characteristics become steeper and some discontinuities occur. These discontinuities are specific for the non-implanted sample and are associated with charging of the fast near interface states (NIToxfast) via a tunneling from the shallow interface states (Dit). The tunneling from the shallow Dit to NIToxfast supress the a.c. response of Dit, which is recovered only after most of the NIToxfast are charged with electrons.

Abstract: The effect of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface on the capacitance of the MOS capacitors is investigated. The Thermal Dielectric Relaxation Current (TDRC) technique and Capacitance-Voltage (C-V) measurements performed at different temperatures and probe frequencies on an N implanted sample and on a virgin sample were employed for this purpose. There are three types of defects located at or near the interface, Dit, NIToxfast and NIToxslow that can be distinguished. Only Dit and NIToxfast respond to the a.c. small, high frequency signal at temperatures above 150K. The separation of Dit from the NIToxfast states have enabled us to study the influence of the excess of interfacial Nitrogen on each of the mentioned defects. It has been found that the N-implantation process fully suppresses the formation of NIToxfast and partially NIToxslow and Dit. Theoretical C-V characteristics were computed, based on the defect distributions determined by TDRC, and compared with the experimental ones showing a close agreement.

Abstract: In this paper the electrical and structural characteristics of n-MOSFETs fabricated on 4H SiC with a process based on nitrogen (N) implantation in the channel region before the growth of the gate oxide are reported for low (5x1018 cm-3) and high (6x1019 cm-3) N concentration at the SiO2/SiC interface. The electron mobility and the free carrier concentration in the MOSFET channel were evaluated by Hall effect measurement. The MOSFETs with the higher N concentration had the best electrical characteristics in terms of threshold voltage and field effect mobility, in spite of a lowering of the electron mobility in the channel. The latter is a negative drawback of the fabrication process that probably can be ascribed to an incomplete recovery of the implantation damage or to a high density of interstitial N atoms present in the channel region. In fact, the MOSFETs with the superior electrical performances were fabricated with the higher N+ dose and the shorter thermal oxidation time. However, no evidence of extended defects, clusters or nano-particles in SiC at the interface with the gate oxide was found in every SiC MOSFETs devices observed by electron transmission microscopy

Abstract: The electrical characteristics of MOSFETs fabricated on 4H-SiC with a process based on N implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface up to 6  1019 cm-3. The field effect mobility improves with increasing N concentration. At room temperature values change from 4 cm2/Vs for the not implanted sample up to 42 cm2/Vs for the sample with the highest N concentration. Furthermore, the field effect mobility increases with temperature and presents values above 60 cm2/Vs at 200 °C. The MOSFETs with the better electrical characteristics (higher mobility, lower threshold voltage, lower subthreshold swing) were fabricated by a low thermal budget oxidation process, thank to the use of a high N implantation dose able to produce an amorphous SiC surface layer. A strong correlation among the increasing of the N concentration at the SiO2/SiC interface, the reduction of the interface state density located near the conduction band and the improvement of the MOSFETs performance was obtained.

Abstract: Phosphorous implanted n+/p diodes have been included in the masks for manufacturing n-MOSFET devices and processed in the same way of source/drain regions. The diode junctions were made by a P+ implantation at 300°C and a post implantation annealing at 1300°C. The diode emitter area was protected by 0.6 m thick CVD oxide during the processing of the MOSFET gate oxide. Three gate oxide processes were taken into account: two of them include a N implantation before a wet oxidation, while the third one was a standard oxidation. Considering the effect on the n+/p diodes, the main difference among the processes were the wet thermal oxidation time that ranged between 180 and 480 min at a temperature of 1100°C. The diode current-voltage characteristics show similar forward but different reverse curves in the temperature range of 25-290°C. Differences in reverse bias voltage as a function of the measurement temperature have been analyzed and are related to the different gate oxidation time. A correlation between the shortest oxidation time and the lower leakage current is presented.