Authors: Jeong Hyun Moon, Jeong Hyuk Yim, Han Seok Seo, Chang Hyun Kim, Do Hyun Lee, Kuan Yew Cheong, Wook Bahng, Nam Kyun Kim, Hyeong Joon Kim
Abstract: We have investigated the electrical and physical properties of the oxidized-SiN with or without post oxidation annealing (POA) in N2 gas. A significant reduction in interface-trap density (Dit) has been observed in the oxidized-SiN with N2 POA for 60 min if compared with other oxides. The reason for this has been explained in this paper.
511
Authors: Ho Keun Song, Jong Ho Lee, Myeong Sook Oh, Jeong Hyun Moon, Han Seok Seo, Jeong Hyuk Yim, Sun Young Kwon, Hyeong Joon Kim
Abstract: Schottky barrier diode (SBD) was fabricated by MOCVD using bistrimethylsilylmethane
(BTMSM, C7H20Si2) precursor. The 4H-SiC substrates which had different
crystallographic characteristics were used for the comparison of the crystallinity effect on the
electrical properties of the SBDs. From the measurement of the reverse I-V characteristics of the
SBDs with micropipes, it is shown that the origin of the main leakage path and early breakdown (or
ohmic behavior in reverse bias) in 4H-SiC SBDs is the grain boundaries caused by the inclusions or
other defects. The best performance of SBD were shown in the epilayer grown at 1440 oC using
high quality substrate, and the breakdown voltage and reverse leakage current were about 450 V
and 10-9 A/cm2, respectively.
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Authors: Han Seok Seo, Ho Geun Song, Jeong Hyun Moon, Jeong Hyuk Yim, Myeong Sook Oh, Jong Ho Lee, Yu Jin Choi, Hyeong Joon Kim
Abstract: Homoepitaxial growth of 4H-SiC epilayer by hot-wall chemical vapor deposition using bis-trimethylsilylmethane (BTMSM, C7H20Si2) precursor was investigated. The growth rate of 4H-SiC was investigated as a function of the growth temperature and source flow rate. The FWHM values of epilayers as the growth temperature and source flow rate also investigated. The growth rate of 4H-SiC epilayer grown by hot-wall CVD was 3.0 μm/h and the background doping level of 4H-SiC epilayer was mid 1015/cm3.
151
Authors: Jeong Hyuk Yim, Ho Keun Song, Jeong Hyun Moon, Han Seok Seo, Jong Ho Lee, Hoon Joo Na, Jae Bin Lee, Hyeong Joon Kim
Abstract: Planar MESFETs were fabricated on high-purity semi-insulating (HPSI) 4H-SiC
substrates. The saturation drain current of the fabricated MESFETs with a gate length of 0.5 μm and a
gate width of 100 μm was 430 mA/mm, and the transconductance was 25 mS/mm. The maximum
oscillation frequency and cut-off frequency were 26.4 GHz and 7.2 GHz, respectively. The power
gain was 8.4 dB and the maximum output power density was 2.8 W/mm for operation of class A at
CW 2 GHz. MESFETs on HPSI substrates showed no current instability and much higher output
power density in comparison to MESFETs on vanadium-doped SI substrates.
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Authors: Ho Keun Song, Han Seok Seo, Jeong Hyun Moon, Jeong Hyuk Yim, Jong Ho Lee, Sun Young Kwon, Hoon Joo Na, Hyeong Joon Kim
Abstract: The authors attempted to grow a semi-insulating SiC epitaxial layer by in-situ vanadium
doping. The homoepitaxial growth of the vanadium-doped 4H-SiC layer was performed by MOCVD
using the organo-silicon precursor, bis-trimethylsilylmethane (BTMSM, [C7H20Si2]) and the
metal-organic precursor, bis-cyclopentadienylvanadium (Verrocene, [C10H10V]). Vanadium doping
effect on crystallinity of epilayer was very destructive. Vanadium-doped epilayers grown on normal
condition had various surface or crystal defects such as micropipes, polytype inclusions. But this
crystallinity degradation was overcome by high growth temperature. For the measurement of the
resistivity of the highly resistive vanadium-doped 4H-SiC epilayers, the authors used the
on-resistance technique. Based on the measurements of the on-resistance of the epilayers using the
current-voltage technique, it is shown that the residual donor concentration of the epilayers was
decreased with increasing partial pressure of verrocene. The resistivity of the vanadium-doped
4H-SiC epilayer was about 107 /cm.
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Authors: Jeong Hyuk Yim, Ho Keun Song, Jeong Hyun Moon, Han Seok Seo, Jong Ho Lee, Hoon Joo Na, Jae Bin Lee, Hyeong Joon Kim
Abstract: 4H-SiC planar MESFETs were fabricated using ion-implantation on high-purity
semi-insulating substrate, and their DC and RF performances were characterized. A modified RCA
method was used to clean the substrate before each procedure. Sacrificial oxide was grown after
channel layer etching to eliminate plasma damage to the gate region. A thin, thermal oxide layer was
grown to passivate the surface and then a thick field oxide was deposited by CVD. The maximum
oscillation frequency of 26.4 GHz and the cut-off frequency of 7.2 GHz were obtained. The power
gain was 8.4 dB and the output power was 2.8 W/mm at 2 GHz.
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