Papers by Author: James D. Scofield

Abstract: In this paper we report the electrical and thermal performance characteristics of 1200 V, 100 A, 200°C (Tj), SiC MOSFET power modules configured in a dual-switch topology. Each switch-diode pair was populated by 2 x 56 mm2 SiC MOSFETs and 2 x 32 mm2 SiC junction barrier Schottky (JBS) diodes providing the 100 A rating at 200°C. Static and dynamic characterization, over rated temperature and power ranges, highlights the performance potential of this technology for highly efficient drive and power conversion applications. Electrical performance comparisons were also made between SiC power modules and equivalently rated and packaged IGBT modules. Even at a modest Tj=125°C, conduction and dynamic loss evaluation for 20kHz, Id=100A operation demonstrated a significant efficiency advantage (38-43%) over the IGBT components. Initial reliability data also illustrates the potential for SiC technology to provide robust performance in harsh environments.

Abstract: Improved AlNi-based ohmic contacts to p-type 4H-SiC have been achieved using low energy ion (Al+)implantation, the addition of a thin Ti layer, and a novel two-step implant activation anneal process. AlNi/Au contacts with and without Ti were studied, which resulted in contact resistivities around 1.8x10-4 -cm2 and 2.0x10-3 -cm2 respectively. Even though these values were higher than those of the Ti/AlNi/W system, which was the focus of previous studies, the reduced anneal temperature (650 to 700°C) implies that Ti/AlNi/Au is a promising composite configuration. Cross-sectional TEM and EDX were used to investigate the interfacial structure of the contacts. One possible mechanism for the improved ohmic contact behavior is that the addition of Au and Ti resulted in a reduction barrier height.

Abstract: Three dimensional models of both single-chip and multiple-chip power sub-modules were generated using ANSYS in order to simulate the effects of various substrate materials, heat fluxes, heat transfer coefficients, and device placement configurations on temperature and thermal stress contours. Alumina, aluminum-nitride, and CVD diamond were compared as substrates. Heat fluxes of 100 to 500 watts/cm2 resulted in SiC device junction temperatures in the range of 350 to 650 K. The predicted maximum operating temperature for a chip, to which 300 watts/cm2 of heat flux was applied, would be 239°C (512 K). In the applied heat flux range, the minimum and maximum Von Mises stress of a simulated single SiC device sub-module was between 1.2 MPa to 2.4 GPa. The maximum shear stress at 300 watts/cm2 was predicted to be 243 MPa. Both the maximum and minimum chip temperature decreased with increasing heat transfer coefficient from 25 to 2500 watts/m2 K. With modest cooling, represented by a heat transfer coefficient (hconv) of 250 watts/m2 K, SiC chips operated at 300 watts/cm2 power density maintained junction temperatures Tj < 400 K. If consistent with simulation results, CVD diamond integrated substrates should be superior to those comprised of AlN or Al2O3. Asymmetric device placement in the multi-chip module proved more effective at avoiding potential hot spots than the symmetric configuration.

Abstract: In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.

Abstract: In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time. The off-state characteristics were evaluated by high temperature reverse bias (HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours. A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for 1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for all tested devices.

Abstract: The performance and characterization of SiC JFETs and BJTs, used as inverter switching devices, in a 2 kW, high temperature, 33 kHz, 270-28 V DC-DC converter has been accomplished. SiC and Si power devices were characterized in a phase shifted H-bridge converter topology utilizing novel high temperature powdered ferrite transformer material, high temperature ceramic filter capacitors, SiC rectifiers, and 10 oz. 220oC polyimide printed circuit boards. The SiC devices were observed to provide excellent static and dynamic characteristics at temperatures up to 300oC. SiC JFETs were seen to exhibit on-resistance trends consistent with temperature-mobility kinetics and temperature invariant dynamic loss characteristics. SiC BJTs exhibited positive temperature coefficients (TCE) of VCE and negative β TCEs, with only a 2-fold increase in on-resistance at 300oC. Both SiC power devices possessed fast inductive switching characteristics with τon and τoff ~100-150 ns when driving the transformer load. The SiC converter characteristics were compared to Si-MOSFET H-bridge operation, over its functional temperature range (30-230oC), and highlights the superiority of SiC device technology for extreme environment power applications.

Abstract: High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.

Abstract: Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.

Abstract: AlNi and Ni2Si based ohmic contacts to p-type 4H-SiC have been produced using low energy ion implantation, a Ti contact layer, and sequential anneals. Low resistivities were promoted by degenerately (>1020 cm-3) doping the surface region of 4H-SiC epilayers via Al+ implantation. High acceptor activation and improved surface morphology was achieved by capping the samples with pyrolized photoresist and using a two-step anneal sequence in argon. Ti/AlNi/W and Ti/Ni2Si/W stacks of varying Ti and/or binary layer thickness were compared at varying anneal temperatures. AlNi based samples reliably and repeatedly achieved specific contact resistivities as low as 5.5 x10-5 ohm-cm2 after annealing at temperatures of 700-1000°C. For the Ni2Si samples, resistivities as low 4.5x10-4 ohm-cm2 were reached after annealing between 750 and 1100°C. Similarly, a set of Ti/AlNi/Au samples, with or without Ge as an additional contact layer, were prepared via the same procedures. In this case, specific contact resistivities as low as 5.0 x10-4 ohm-cm2 were achieved after annealing the Ti/AlNi/Au samples between 600 and 700°C for 30 minutes in a dynamic argon atmosphere or under high vacuum. The lowest resistivities were realized using thicker (~ 40 nm) Ti layers. I-V analysis revealed superior linear characteristics for the AlNi system, which also exhibited a more stable microstructure after anneal. SIMS and RBS were used to analyze the stability of the stacks subsequent to thermal treatment. AFM analysis demonstrated the superiority of photoresist capping over alternatives in minimizing surface roughness. Linear ohmic behavior after significantly reduced anneal temperature is the main observation of the present study.

Abstract: Nickel ohmic contacts to p-type epitaxial and heavily implanted 4H-SiC are described. Room and elevated temperature results are presented. Elevated temperature measurements of specific contact resistance are compared to theoretical calculations. The calculations require the acceptor doping concentration and the contact’s barrier height. Epitaxial material has a known acceptor value thereby allowing the barrier height to be deduced by requiring agreement between the calculated and measured values of the contact resistance. Calculations of the contact resistance for implanted material use the barrier height from the epitaxial results along with a variable activated acceptor doping concentration which is adjusted to give agreement with measured room temperature specific contact resistances. Specific contact resistances as low as 7x10-6 ohm-cm2 fabricated on the Si face have been obtained to epitaxial 4H p-type material whereas contacts to implanted material result in much larger contact resistance values of 4x10-5 ohm-cm2. These results, when compared to theoretical calculations, indicate that activated acceptor doping concentrations in heavily implanted material are on the order of 2% of the implant concentration.