Authors: Konstantinos Zekentes, Katerina Tsagaraki, Maria Androulidaki, Maria Kayambaki, Antonis Stavrinidis, Hervé Peyre, Jean Camassel
Abstract: The purpose of the present study is to determine the appropriate physical characterization methods for evaluating material quality changes during the fabrication steps of a typical 4H-SiC Static Induction Transistors (SITs). The most important fabrication step in terms of material quality is the gate implantation and post-implantation annealing. For the purposes of the initial investigation, separate “witness” samples from the processed sample have been used for evaluating implantation and post-implantation annealing. Secondary Ion Mass Spectroscopy (SIMS), optical transmission, room-temperature photoluminescence (RTPL), High Resolution X-Ray diffraction (HRXRD) and C-V measurements with Hg-probe and electrochemical (ECV) cells have been investigated in the frame of the present study. HRXRD and ECV have been proved particularly suitable for characterizing the implanted layers.
589
Authors: Georgios Zoulis, J.W. Sun, Remigijus Vasiliauskas, Jean Lorenzzi, Hervé Peyre, Mikael Syväjärvi, Gabriel Ferro, Sandrine Juillaguet, R. Yakimova, Jean Camassel
Abstract: We report on n-type 3C-SiC samples grown by sublimation epitaxy. We focus on the low temperature photoluminescence intensity and show that the presence of a first conversion layer, grown at low temperature, is not only beneficial to improve the homogeneity of the polytype conversion but, also, to the LTPL signal intensity. From the use of a simple model, we show that this comes from a reduced density of non-radiative recombination centers.
149
Authors: Aurore Constant, Nicolas Camara, Josep Montserrat, Esther Pausas, Jean Camassel, Philippe Godignon
Abstract: Rapid Thermal Processing (RTP) has been evaluated as an alternative to the conventional furnace process for the gate oxide formation of SiC lateral MOSFETs. We show that this innovative oxidation method has not only the advantage to significantly reduce the thermal budget compared to classical oxidation, but also produces a significant improvement of MOSFET performance when using N2O as oxidizing gas. Studying different surface preparation before gate oxidation, we demonstrate that in-situ surface preparation by H2 annealing increases considerably the channel mobility and also the electrical stability with respect to constant bias stress at low-field.
500
Authors: Teddy Robert, Maya Marinova, Sandrine Juillaguet, Anne Henry, Efstathios K. Polychroniadis, Jean Camassel
Abstract: Both 3C and 6H stacking faults have been observed in a low doped 4H-SiC epitaxial layer grown in a hot-wall CVD reactor on a heavily doped (off-axis) 4H-SiC substrate. They appear differently on the different parts of sample, with energetic dispersion ranging from 3.01 eV to 2.52 eV. Since they behave as natural type-II quantum wells in the 4H-SiC matrix, the thickness dependence of the excitonic recombination is investigated using the standard effective mass approximation. The results are discussed in terms of built-in electric field and inter-well coupling effects.
314
Authors: Maya Marinova, Ariadne Andreadou, Jian Wu Sun, Jean Lorenzzi, Alkyoni Mantzari, Georgios Zoulis, Nikoletta Jegenyes, Sandrine Juillaguet, Véronique Soulière, Gabriel Ferro, Jean Camassel, Efstathios K. Polychroniadis
Abstract: The current communication focuses on the influence of a post-growth annealing on the evolution of defects inside (111) 3C-SiC layers grown by the Vapour Liquid Solid (VLS) mechanism in SiGe melts on Si-face on- and off axis 6H-SiC substrates. The layers are studied by Transmission Electron Microscopy (TEM) and Low Temperature Photoluminescence (LTPL). It was found that the growth on off-axis substrates results in a 3C-SiC layer containing mainly stacking faults (SFs) and microtwins (MT). The density of MT lamellae and SFs reduces in the layers grown on the on-axis substrate compared to off-axis substrate. In the layers grown on off-axis substrates the annealing strongly reduces the density of SFs inclined to the 3C/6H-SiC interface. Additionally, 3C to 6H polytypic transformation appears only at the interface, most probably starting from substrate step edges. This was only seen on off-axis seed since the step edges are more.
241
Authors: Georgios Zoulis, Jian Wu Sun, Irina G. Galben-Sandulache, Guoli L. Sun, Sandrine Juillaguet, Thierry Ouisse, Didier Chaussende, Roland Madar, Jean Camassel
Abstract: We present the results of an optical investigation performed using low temperature photomuminescence and Raman spectroscopy on bulk 3C-SiC samples grown with the Continuous-Feed Physical Vapor Transport technique, using a small diameter neck to filter the defects and improve the as-grown material.
169
Authors: Maya Marinova, Alkyoni Mantzari, Jian Wu Sun, Jean Lorenzzi, Ariadne Andreadou, Georgios Zoulis, Sandrine Juillaguet, Gabriel Ferro, Jean Camassel, Efstathios K. Polychroniadis
Abstract: The current communication focuses on the investigation of 3C-SiC layers grown by the Vapour-Liquid-Solid mechanism on on-axis Si-face 6H-SiC substrates in SiSn melts with different compositions and at different growth temperatures. The layers are studied by Transmission Electron Microscopy and Low Temperature Photoluminescence. It was found that for melts with Sn concentration higher than 60 at% large Sn-related precipitates are formed. The depth distribution of the Sn precipitates strongly depends not only on the melt composition but also on the growth temperature. Their formation strongly influences the stacking fault density and the dopant incorporation in the layers. Lower Sn concentrations combined with higher growth temperatures should result in 3C-SiC layer with enhanced structural quality.
165
Authors: Nicolas Camara, Alessandra Caboni, Jean Roch Huntzinger, Antoine Tiberj, Narcis Mestres, Philippe Godignon, Jean Camassel
Abstract: Epitaxial graphene growth is significantly different depending on the polarity of the 6H-SiC surface: Si- or C-face. On the Si-face, a uniform coverage of few layers on the whole sample can be obtained, but with electrical properties disturbed by the presence of a Carbon-rich buffer layer at the interface. On the contrary, on the C-face, we demonstrated that almost free-standing very large monolayers of graphene can be obtained by covering the sample with a graphitic cap during the growth.
581
Authors: Aurore Constant, Nicolas Camara, Philippe Godignon, Maxime Berthou, Jean Camassel, Jean Manuel Decams
Abstract: Rapid Thermal Processing (RTP) has been evaluated as an alternative to conventional furnace technique for oxidation of 4H- and 3C-SiC. We show that the growth of the SiO2 films in a RTP chamber is orders of magnitude faster than in a conventional furnace. As well as being fast, this process leads to oxide films with quality comparable or even better than the one grown in classical furnaces. Studying different gas for oxidizing and annealing ambient, we demonstrate that SiO2/SiC interface is significantly improved when using N2O instead of O2 or even N2-O2 dilution.
817
Authors: Georgios Manolis, Georgios Zoulis, Sandrine Juillaguet, Jean Lorenzzi, Gabriel Ferro, Jean Camassel, Kęstutis Jarašiūnas
Abstract: Thin 3C-SiC(111) epilayers grown on 6H-SiC(0001) substrate by VLS and CVD procedures were studied by low temperature photoluminescence (LTPL) and nonlinear optical techniques at room and low temperatures. Free carrier density ((0.3-7)×1017 cm-3) and nitrogen concentration (4×1016 cm-3) in the layers were determined from Raman and LTPL data. Investigation of non-equilibrium carrier dynamics by using transient grating and free carrier absorption techniques provided an ambipolar diffusion coefficient Da (~2.5 cm2/s) and carrier lifetime τR (2-4 ns) values at room temperature. The temperature dependences of Da and τR in 40-300 K range revealed the scattering processes in high density plasma as well the impact of defects.
443