Papers by Author: Jeff B. Casady

Abstract: In this work we present the epitaxial growth of 4H-SiC on 100mm 4° off-axis substrates grown in a multi-wafer CVD planetary reactor. Highly uniform epitaxial layers having thickness and doping uniformities of 1.7% and 1.4% respectively were grown in the production reactor with optimized process conditions at 8µm/hr and 30µm/hr growth rates. Process optimizations resulted in epitaxial layers with surface roughness (RMS) of 0.32nm. Epitaxial layers with a thickness of 53µm grown with a 30µm/hr growth process had minimal degradation in surface roughness (RMS of 0.39nm).

Abstract: An all SiC 600V / 6 m hermetic half-bridge power module has been developed to operate at ambient temperatures of 200oC and with junction temperatures near 250oC. The modules use SiC trench JFET technology and can output over 100A at Tj=250oC. Double pulsed switching was performed up to temperatures of 150oC with a measured total switching energy of 0.73mJ

Abstract: This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device’s intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SemiSouth’s SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.

Abstract: Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.

Abstract: This work presents the progress in developing an all SiC based power module for use in high frequency and high efficiency applications. Using parallel combinations of 1200V enhancement mode SiC VJFETs (36mm2) and Schottky diodes (23mm2), a total on-resistance of only 10mOhm (2.7m-cm2) was achieved at ID=100A in a commercially available standard module configured as a half-bridge circuit. Careful attention to module layout, gate driver design, and the addition of optimized snubbers resulted in excellent switching waveforms with low total switching losses of 1.25mJ when switching 100A at 150oC.

Abstract: Recently 63 m, 100 m, and 125 m 1200 V normally-off SiC VJFETs have become commercially available and 99% efficiency has been demonstrated in a single-phase solar inverter using these components [1]. They exhibit low specific on-resistance (3 m∙cm2), high saturation current density (1000 A∙cm-2), and low switching losses. For some applications, including 30 to 100 kW inverter modules and those requiring high surge current capability, larger die size is required. This paper reports the static and dynamic performance of 15 mm2 1200 V normally-off VJFETs with 25 m on-resistance and 120 A saturation current at 25 °C.

Abstract: We report here an anisotropic increase in SiC bulk resistivity by annealing at 1150 °C, and discuss the implications for SiC devices. The increase in resistivity is resistivity dependent and can be (at least) partially reversed by a subsequent anneal at higher temperature. Ideal device performance is achievable with appropriate annealing steps during device processing.

Abstract: 4H Silicon Carbide (4H-SiC) has a great potential for low-loss power devices due to its superior electrical properties. However, the increase in demand for the power devices requires high quality SiC substrates and epitaxial layers. Mercury probe Capacitance Voltage (Hg CV) measurement is a well known procedure to characterize epi layers grown on SiC substrates, due to its non-destructive technique. However, careful calibration of the tool is very important for repeatable and accurate measurements. Here we present very close repeatability of Hg CV within 2.4% (standard deviation 0.7%), between different Solid State Measurements (SSM) setups compared with Ni Schottky (NiS) CV. In addition to growing uniformly doped epi layers, high surface quality of the epi layer is also needed for improved device performance. Improved process conditions resulted in a smooth epi with a surface roughness Ra 1.2 nm for a 6 µm thick epi layer. Molten Potassium Hydroxide (KOH) etching analysis also revealed a significant correlation between the surface roughness and epi defects.

Abstract: SiC Lateral Trench JFET (LTJFET) technology is demonstrated as a promising candidate for use in high-temperature wireless telemetry systems. 4H-SiC LTJFETs were designed, fabricated and characterized for DC, and small-signal AC and RF performance at different case temperatures. Four-fold drain current reduction was observed at 460°C as compared to RT measurements. The measured threshold voltage shift was less than 2.3 mV/°C from 21°C to 460°C. A simple common source amplifier built using a fabricated device demonstrated stable small-signal AC performance after 100 hrs of operation at 450°C. Small-signal RF measurements were carried out on the packaged devices at different temperatures. GMax above 8 dB was measured over the L-band frequency range at RT. The average degradation of small-signal power gain measured at f=250 MHz did not exceed 0.0125 dB/ °C over the temperature ranging from 21°C to 365°C.

Abstract: In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.