Papers by Author: Michael S. Mazzola

Abstract: The two-dimensional device simulator, MediciTM, was used to simulate 4H silicon carbide (4H-SiC) n-channel power metal semiconductor field effect transistors (MESFETs) with 0.5 µm gate length with and without p-type buffer layer between the n-channel and the semi-insulating (SI) substrate. The devices, which have previously been fabricated and characterized experimentally, have ion-implanted n+ source and drain ohmic contact regions. The simulations were performed with transient 30 V amplitude symmetrical triangular pulse with 30 s pulse width. Simulations show that hysteresis in drain I-V curves of MESFETs is due to substrate traps and source/drain implant damage traps. The hysteresis is caused by trapping and emission of channel electrons by the traps as VDS rises from 0 V to VDS(max) and as VDS falls from VDS(max) back to 0 V. This leads to difference in trap occupation, and hence difference in channel electron concentration as VDS rises and falls. This finally leads to difference in drain-source current (IDS) at a given VDS for a given VGS as VDS rises and falls, giving rise to the hysteresis in the I-V curves.

Abstract: The design of analog integrated circuits, for instance, the operational amplifiers, have been widely perfected with devices and processes available in silicon. However, analogous circuits have been the subject of research in Silicon Carbide (SiC). Among SiC devices, 4H-SiC Lateral-Trench JFET (LTJFET) transistor offers advantages and new opportunities to make affordable and reliable analog integrated circuits for harsh environment. In this paper: (1) SiC LTJFET is characterized for modeling and simulation, (2) effect of temperature variation on SiC LTJFET threshold voltage and small signal parameters are reported, (3) gain performance and small signal parameters of the basic analog circuit block, Common Source (CS) amplifier, based on the variation of the load transistors threshold voltage (Vth) are studied and analyzed, and (4) frequency and transient response of the cascoded CS amplifier (CS-Cas) are reported.

Abstract: In this work, we report the most recent reliability results of the 1200-V SiC vertical-channel JFETs (VJFETs) under reverse and forward bias of the gate-source diode at temperatures up to 200 °C. The preliminary results indicate that continuous forward bias stress of the gate-source diode at 200 °C for 112 hours produced no observable change in the forward conduction or transient or reverse blocking characteristics of the vertical-channel JFET. This preliminary result suggests that devices based on this structure, such as the enhancement-mode (normally off) SiC VJFET, may not be effected by the recombination enhanced defect creation process and the associated increase in on-resistance, related to body-diode conduction in the SiC DMOSFET and the SiC lateral-channel depletion-mode JFET. Since the vertical-channel JFET has no body diode, no degradation is possible from the reverse conduction mode of operation.

Abstract: SiC Lateral Trench JFET (LTJFET) technology is demonstrated as a promising candidate for use in high-temperature wireless telemetry systems. 4H-SiC LTJFETs were designed, fabricated and characterized for DC, and small-signal AC and RF performance at different case temperatures. Four-fold drain current reduction was observed at 460°C as compared to RT measurements. The measured threshold voltage shift was less than 2.3 mV/°C from 21°C to 460°C. A simple common source amplifier built using a fabricated device demonstrated stable small-signal AC performance after 100 hrs of operation at 450°C. Small-signal RF measurements were carried out on the packaged devices at different temperatures. GMax above 8 dB was measured over the L-band frequency range at RT. The average degradation of small-signal power gain measured at f=250 MHz did not exceed 0.0125 dB/ °C over the temperature ranging from 21°C to 365°C.

Abstract: In this work we have demonstrated the high-temperature operations of 600 V/50 A 4HSiC vertical-channel junction field-effect transistors (VJFETs) with an active area of 3 mm2. Specific-on resistance (RONSP) in the linear region of a single die is less than 2.6 mW.cm2 while the drain-source current is over 50 A under a gate bias (VGS) of 3 V. A reverse blocking gain of 54 is obtained at gate bias ranging from -13 V to -23 V and drain-source leakage current (IRDS) of 200 μA. To demonstrate the use of SiC VJFETs for high-power applications, eight 3 mm2 SiC VJFETs are bonded in a high current 600-V module. RONSP in the linear region of these eight-paralleled SiC VJFETs is 2.8 mW.cm2 at room temperature and increased to 5.35 mW.cm2 at an ambient temperature of 175 °C in air, corresponding to a shift of 0.61%/°C from room temperature to 175 °C. Meanwhile, the forward current is over 360 A at room temperature and reduces to 188 A at 175 °C at drain-source bias (VDS) of 5.25 V and VGS of 3 V.

Abstract: In this work we report the most recent high-temperature long-term reliability results of the 600 V/14 A, 4H-SiC vertical-channel junction field-effect transistors (VJFETs). Two groups (A and B) devices were subjected to different thermal and electrical stresses. One device (Group A) reached 12,000 hours of continuous switching without a single failure. Four devices in Group A were thermally stressed at 250 °C over 4,670 hours in air, for which standard deviation of the specific on-resistance (RONSP) in linear region at gate bias (VGS) of 3 V were < 4.1% throughout the entire duration time. The off-state characteristics were evaluated by high temperature reverse bias (HTRB) tests. Three devices (Group A) were biased at 50% rated BVDS at 250 °C for 2,278 hours. A higher reverse bias at 80 % rated BVDS was then applied to 14 devices (group B) at 200 °C for 1,000 hours. Variations of the leakage current were negligible throughout the entire HTRB test for all tested devices.

Abstract: Epitaxial growth of 3-in, 4° off-axis 4H SiC with addition of HCl has been presented. Good surface morphology with a low defect density has been obtained, even for epi thickness of 38 µm. Comprehensive characterization techniques conducted on the epi material obtained in this process have independently confirmed the high purity and low density of crystalline imperfections. Low temperature PL displays clear free exciton I77 recombination while no L1 line is discernable. DLTS measurements have confirmed a low concentration of Z1/2 and EH6/7 below or in the range of 1011 cm-3. Time resolved PL at room temperature performed on a 38 µm thick epi wafer gives long carrier lifetime in the range of 1.5 to above 5 µsec. PiN diodes with diode area up to 25 mm2 have demonstrated blocking voltages above 900V, with a max electric field of above 2.5 MV/cm.

Abstract: The purpose of this paper is to present an all-SiC switched AC-DC converter using active power factor correction. The typical boost-converter approach is employed using continuous conduction mode. A SiC Schottky barrier diode performs the free-wheeling diode function, and a 600 V, 0.12 % SiC vertical junction field effect transistor performs the switching function under the control of a Fairchild ML4821 integrated circuit. The converter is operable off-line over the full universal voltage range (85-260 VAC), but it was optimized for a 400-600 W application operating at 208 VAC. Results are presented that demonstrate extremely high efficiency at a switching frequency of 500 kHz, the highest operating frequency of the ML4821.

Abstract: In this paper we present highly uniform SiC epitaxy in a horizontal hot-wall CVD reactor with wafer rotation. Epilayers with excellent thickness uniformity of better than 1% and doping uniformity better than 5% are obtained on 3-in, 4° off-axis substrates. The same growth conditions for uniform epitaxy also generate smooth surface morphology for the 4° epiwafers. Well controlled doping for both n- and p-type epilayers is obtained. Abrupt interface transition between n- and pdoped layers in a wide doping range is demonstrated. Tight process control for both thickness and doping is evidenced by the data collected from the epi operations. The average deviation from target is 2.5% for thickness and 6% for doping. PiN diodes fabricated on a standard 3-in, 4° epiwafer have shown impressive performance. More than half of the 1 mm2 devices block 1 kV (2.3 MV/cm) with a low leakage current of 1 μA.

Abstract: Dielectric charges and charge stability were compared in different dielectrics formed on SiC by different processing techniques. The concentration and transient behavior of the interface and trapped charges were investigated. Strong hysteresis and flat-band voltage drift under applied bias were observed in some of the samples. They are attributed to the trapping of the charge injected in the dielectrics. Differences in charge injection, charge trapping, and capture/emission of carriers by interface traps were pronounced for the investigated SiO2 and Si3N4 dielectrics.