Papers by Author: Patrick Chaudouët

Abstract: The influence of nitrogen impurity on the stabilization of 3C-SiC polytype has been studied during vapour-liquid-solid (VLS) growth on 6H-SiC(0001) seed with Si-Ge melt. By changing the partial pressure of N2 during growth, it was found that the proportion of 3C-SiC inside the grown material increases with N2 partial pressure. 6H inclusions are only found for high purity (low N2 content) conditions. The possible interactions proposed to explain this effect are divided in two effects: i) lattice parameter modification and ii) surface induced lateral enlargement variation. A combination of both effects is suspected.

Abstract: Like on 6H-SiC substrates, 3C-SiC islands precipitation was found to be the initial stage of the VLS growth of 3C-SiC layers on 4H-SiC surfaces. This precipitation happens between 1100 and 1200°C with a heating rate of 2.8°C.s-1, without addition of propane. The islands size increases in a similar manner whether the final temperature increases (for a given heating rate) or the heating rate decreases (for a given final temperature). This enlargement can give rise to a complete cubic layer for the highest temperatures or the slowest heating rates. It is suggested that the carbon atoms involved in the enlargement process (after the nucleation) come from the graphite crucible.

Abstract: We report on the heteroepitaxial growth of 3C-SiC layers by Vapor-Liquid-Solid (VLS) mechanism on various α-SiC substrates, namely on- and off-axis for both 4H and 6H-SiC(0001), Si and C faces. The Si-Ge melts, which Si content was varied from 25 to 50 at%, were fed by 3 sccm of propane. The growth temperature was varied from 1200 to 1600°C. It was found that singledomain 3C-SiC layers can be obtained on 6H-SiC off and on-axis and 4H-SiC on-axis, while the other types of substrate gave twinned 3C-SiC material. As a general rule, one has to increase temperature when decreasing the Si content of the melt in order to avoid DPB formation. It was also found that twinned 3C-SiC layers form at low temperature while homoepitaxy is achieved at high temperature.

Abstract: The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC support to obtain a “quasi-wafer” is an attractive way for lowering the cost of silicon carbide wafers. Such a process needs high quality polycrystalline substrates, with controlled and high-level bulk properties (thermal conductivity, electrical resistivity) and with very low surface roughness and surface bowing. Currently, polycrystalline SiC wafers which are available are siliconized SiC or CVD processed SiC wafers. Siliconized ceramic wafers are very heterogeneous (mixture of 3C, 6H, 15R and silicon), while CVD ones are of better quality (homogeneous and textured 3C). However neither the siliconized SiC nor the CVD SiC can be CMP polished with low roughness over large dimension. In this paper, wafers with large and textured grains (> 1cm) are processed and characterized. The polishing of such structures is studied and optimized to obtain low surface roughness. To meet these requirements high temperature processes used for single crystal growth were selected. Structural investigations performed on the grown ingots showed an important influence of the used seed since no preferential crystallographic orientation was observed during the growth. The final polishing quality was of high level but step heights were observed between grains.