Papers by Author: Peter Friedrichs

Abstract: Since SiC VJFETs are believed to offer extremely fast turn on and turn off processes it is important to understand how these transients are tailored by the layout. Regarding the basic layouts two main topologies are under investigation today – structures with the well known SIT layout with purely vertical current flow and lateral vertical concepts where the current flow through the channel is in lateral direction and the vertical current flow takes place in the drift region only. In this paper we will focus on differences in the electric characteristics of both structures and the relation of the dynamic behavior to the topology and the layout of the switches. For the analysis, 1200V VJFETs based on the two basic topologies were manufactured having approximately the same total and active device area. It turns out that the SIT switches under investigation suffer from a high internal gate resistance in the p-doped layers and a relatively high gate drain capacitance.

Abstract: In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.

Abstract: The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.

Abstract: After the successful introduction of silicon carbide Schottky-Barrier diodes in 2001, next commercial devices will be switching components. The development focus is targeted to MOSFETs and VJFETs. Regarding VJFETs, a promising device was presented several years ago and tested successfully in several applications. Since the unconventional device structure does not allow the use of classical JFET models, a new electro-thermal model was developed, taking into account the features of the design as well as the targeted enlarged range of operating temperatures.

Abstract: In this work, the electrical characteristics and the reliability of 80nm thick deposited oxides annealed in NO and N2O on the 4H-SiC Si-face for gate oxide application in MOS devices is analyzed by C-V, I-V measurements and by constant current stress. Compared to thermally grown oxides, the deposited oxides annealed in N2O or NO showed improved electrical properties. Dit-values lower than 1011cm-2eV-1 have been achieved for the NO sample. The intrinsic QBD-values of deposited and annealed oxides are one order of magnitudes higher than the highest values reported for thermally grown oxides. Also MOSFETS were fabricated with a channel mobility of 20.05 cm2/Vs for the NO annealed deposited oxide. Furthermore annealing in NO is preferred to annealing in N2O regarding µFE- and QBD-values.

Abstract: Today a main focus in high efficiency power electronics based on silicon carbide (SiC) lies on the development of an unipolar SiC switch. This paper comments on the advantages of SiC switching devices in comparison to silicon (Si) switches, the decision for the SiC JFET against the SiC MOSFET, and will show new experimental results on SiC JFETs with focus on the production related topics like process window and parameter homogeneity which can be achieved with the presented device concept. Due to material properties unipolar SiC switches have, other than their Si high voltage counterparts, very low gate charge, good body diode performance, and reduced switching losses because of the potential of lower in- and output capacitances. The most common unipolar switch is the MOSFET. However, the big challenge in the case of a SiC MOSFET is the gate oxide. A gate oxide on SiC that provides adequate performance and reliability is missing until now. An alternative unipolar switching device is a normally-on JFET. The normally-on behavior is a benefit for current driven applications. If a normally-off behavior is necessary the JFET can be used together with a low voltage Si MOSFET in a cascode arrangement. Recently manufactured SiC JFETs show results in very good accordance to device simulation and demonstrate the possibility to fabricate a SiC JFET within a mass production. A growing market opportunity for such a SiC switch becomes visible.

Abstract: The reliability of thermal oxides grown on n-type 4H-SiC C(000-1) face wafer has been investigated. In order to examine the influence of different oxidation atmospheres and temperatures on the reliability, metal-oxide-semiconductor capacitors were manufactured and the different oxides were characterized by C-V measurements and constant-current-stress. The N2O-oxides show the smallest flat band voltage shift compared to the ideal C-V curve and so the lowest number of effective oxide charges. They reveal also the lowest density of interface states in comparison to the other oxides grown on the C(000-1) face, but it is still higher than the best oxides on the Si(000-1) face. Higher oxidation temperatures result in smaller flat band voltage shifts and lower interface state densities. Time to breakdown measurements show that the charge-to-breakdown value of 63% cumulative failure for the N2O-oxide on the C(000-1) face is more than one order of magnitude higher than the highest values measured on the Si(000-1) face. Therefore it can be concluded that a smaller density of interface states results in a higher reliability of the oxide.

Abstract: In this paper, we present results of epitaxial layer deposition for production needs using our hot-wall CVD multi-wafer system VP2000HW from Epigress with a capability of processing 7×3” or 6×100mm wafers per run in a new 100mm setup. Intra-wafer and wafer-to-wafer homogeneities of doping and thickness for full-loaded 6×100mm and 7×3” runs will be shown. Results on Schottky Barrier Diodes (SBD) processed in the multi-wafer system will be given. Furthermore, we show results for n- and p-type SiC homoepitaxial growth on 3”, 4° off-oriented substrates using a single-wafer hot-wall reactor VP508GFR from Epigress for the development of PiN-diodes with blocking voltages above 6.5 kV. Characteristics of n- and p-type epilayers and doping memory effects are discussed. 6.5 kV PiN-diodes were fabricated and electrically characterized. Results on reverse blocking behaviour, forward characteristics and drift stability will be presented.

Abstract: We have carefully investigated a number of more than 120 selected chips fabricated on one wafer, by I-V measurements at two different precisely controlled temperatures and precision CV measurements at room temperature. From these measurements the net-doping concentration, the C-V (flat-band) barrier ΦCV, the ideality n, the apparent Richardson constant Aapp and the apparent I-V barrier Φapp have been extracted for each chip. An extremely unique C-V barrier was determined showing a relative standard deviation (sigma over mean) of only 0.086%. Moreover, the average ideality n was found to be as low as 1.028 exhibiting a relative standard deviation of only 0.35%. A clear linear correlation (ρ2 = 0.968) between ideality n and apparent I-V barrier was observed. The effective Richardson constant A** of 4H-SiC in 〈0001〉 directions could therefore be extracted to be most likely in the interval 70 Acm-2K-2 < A** < 80 Acm-2K-2.

Abstract: SiC power MOSFETs are attractive electronic power switches for innovative power supply and motor drive solutions. The paper discusses this statement and specifies market segments offering the best chances for a commercialization. Due to well-known difficulties in achieving adequate channel conductivity, a lot of SiC-MOSFET publications focus on the channel mobility. However, for a power MOSFET this is only one important parameter affecting the performance. Other characteristics have to be considered too for an honest evaluation: transfer characteristics and blocking capability over the standard operation temperature range, handling of gate oxide stress and related reliability issues, capability of paralleling, dynamic stability, body diode characteristics, reproducibility of the fabrication process and device size. Various attempts have been made in recent years in order to address these features. Approaches differ in the use of different crystal orientations and polytypes, accumulation or inversion channel, implanted or epitaxially grown channels and novel oxidation techniques. Worldwide a trend to the planar DIMOS concept can be observed. Our present results are shown for a power SiC MOSFET designed for 10 A / 1200 V. Key data are a specific on-resistance of 12 m1cm2, the desired low but positive increase of the onresistance with temperature, static avalanche (20 mA DC @1574 V), short-circuit stability at 600 V for 20 9s and robust switching behavior.