Papers by Author: R. Navickas

Abstract: CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

Abstract: Hybrid pixel sensors (detectors) have shown to be a valid alternative to other types of Xray imaging devices due to their high sensitivity, linear behavior and wide dynamic range, and low noise. One important feature of these devices is the fact that detectors and readout electronics are manufactured separately. The charge created by the interaction of X-ray photons in the sensor is very small and has to be amplified in a low-noise circuit before any further signal processing. The signal induced on the electrodes of the sensor is transferred to the readout chip, where it is integrated in a charge sensitive amplifier. The issue reviews on physical principles of operation and design of the hybrid pixel sensors developed on the basis of the silicon CMOS and GaAs MESFETtechnologies. The authors have designed GaAs charge sensitive amplifiers for hybrid pixel detectors and show the results of a simulation.

Abstract: The analysis of technological trends nanoelectromechanical systems and processes of self-formation micro- and nanostructures in manufacturing MEMS/NEMS have been made and the requirements have been formulated. The results of modeling geometry nanostructures and the implementation of self-formation processes for creating new technologies of manufacturing MEMS/NEMS have also been presented.

Abstract: A model of the evolution geometry technological masks and underlaying layers in the lateral etching processes is created for analysis and design of new self-alignment and self-formation technologies semiconductor devices and integrated circuits. The results of the simulation for the different configurations masks and selectivities of the underlaying layers have been presented.

Abstract: The analysis for basic processes of self-formation microstructure in technologies of manufacturing semiconductor devices and integrated circuits (IC) have been made and the requirements have been formulated. The results of the implementation of self-formation processes for creating new technologies of manufacturing semiconductor devices and IC have been presented.

Abstract: The model of the evolution of nano- and microstructures in the self-formation process of underetching (lateral etching) layers was created for analysis and design of new self-alignment and self-formation technologies semiconductor devices and integrated circuits. The program was realized on the basis of a personal computer with the processor INTEL PENTIUM 4 and MATLAB 5.3 software. The results of the simulation were given for the different initial configurations of nanostructures. The experimental investigations evolution of microstructures in lateral etching processes of amorphous and polycrystalline films were performed and the results presented.