Papers by Author: Ryouji Kosugi

Abstract: This paper reports an EDMR (electrically detected magnetic resonance) observation on 4H-SiC(000-1) “C face” MOSFETs. We found a new strong EDMR signal in wet-oxidized C-face 4H-SiC MOSFETs, which originates from intrinsic interface defects on C-face SiC-SiO2 structures.

Abstract: The surface and interface roughness of SiO₂/4H-SiC(0001) was investigated in terms of Si emission from the interface and oxidation induced compressive stress. It was demonstrated that the SiO₂ surface roughness growth was strongly related with oxidation mechanism, as well as SiO₂ on Si substrate. A model for surface roughening was proposed with areal Si density and Young’s modulus to inclusively explain the surface roughness of SiO₂ on various substrates.

Abstract: We discuss the results of electrically detected magnetic resonance (EDMR) spectroscopy on SiC-SiO₂ interfaces interacting with hydrogen and nitrogen. Using EDMR, three types of 4H-SiC MOSFETs, which were prepared by dry oxidation (“Dry” sample), post hydrogen anneal (“Hydrogen” sample), and post nitridation anneal (“Nitrogen” sample), were examined in the temperature range of 4–300 K. These samples revealed several different results from the earlier ESR (electron spin resonance) and EDMR studies on SiC-SiO₂ interfaces. The most significant finding was the high-density doping of nitrogen into the channel region after the post nitridation anneal. The incorporated nitrogen donors were observed as the “Nh” EDMR signal at 4–20 K. Roles of these nitrogen donors are discussed in correlation with the electrical properties of SiC MOSFETs.

Abstract: We present an electrically detected electron-spin-resonance (ESR) study on SiO2-SiC interface regions of n-channel lateral 4H-SiC MOSFETs with hydrogen annealing. This characterization technique can reveal electrically active defects that interact with channel currents of the MOSFETs. The defects were observed at 20 K, and were labeled “PH0” and “PH1”, one of which (PH1) exhibited a 1H hyperfine splitting of 5.3 mT.

Abstract: The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.

Abstract: We have fabricated the four pn-type junction TEGs (Test Element Groups) having different structure. Those TEGs are close to the double-implanted (Di) MOSFETs, step by step from the simple pn diode. Voltage-current (V-I) characteristics of the hundred TEGs having p-well structure show similar blocking characteristics of those of simple pn diodes on the same wafer. This indicates that the p-well structure itself does not cause a significant deterioration on the blocking yield. On the other hand, the yield is significantly influenced by the annealing condition for ion-implanted layer. The oxide-related hard breakdown on the JFET region dominates the blocking yield. The reach-through breakdown of the TEGs having the n+ region within each p-well becomes largely suppressed by the high-temperature and short-time annealing.

Abstract: The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm2 and excellent dynamic characteristics.

Abstract: Dislocations in a substrate wafer of 4H-SiC with an epi-layer were observed using technique of monochromatic synchrotron X-ray topography in a grazing incidence geometry. Six different Burgers vectors of basal plane dislocations and threading edge dislocations were identified by changing the Bragg reflections, and by analysis of images of dislocation. We identify some relations of the Burgers vector and the dislocation contrast observed for g=11 2 8. Some of these relationships are discussed in this report.

Abstract: 4H-SiC substrate wafers with epi-layers were observed using monochromatic synchrotron X-ray topography in grazing incidence geometries, to investigate the defects in the epi-layer. Misfit dislocations with b=+1/3[11 2 0] caused by the difference in lattice parameter between the epi-layer and the substrate were observed. The misfit dislocations are located near the interface as edge dislocations, and appear at the top surface as screw dislocations on basal planes. It was observed that more than half of them were introduced from the growing epi-layer surface. The misfit dislocations and some screw dislocations with b=+1/3[11 2 0] are observed to remain as basal plane dislocations at the surface, while other basal plane dislocations were converted to threading edge dislocations in the epi-layer.

Abstract: A passivation annealing in nitric oxide (NO) ambient significantly reduces the interfacial defects of the SiO2/4H-SiC interface and improves the inversion MOS channel mobility. Effects of the nitridation in NO ambient become more pronounced at high temperatures in general. However, the maximum process temperature in a standard hot-wall oxidation furnace is restricted around 1200oC due to the softening point of quartz. Meanwhile, by use of a cold-wall oxidation furnace, high temperature and short time thermal processes become possible. In this study, we have developed an extremely high temperature (>1400oC) rapid thermal processing for the gate oxidation in the 4H-SiC DIMOSFET fabrication process. The peak MOS channel mobility of lateral MOSFETs on the DIMOSFET chip shows as high as 19cm2/Vs. The specific on-resistance of the device was 12.5m
cm2 and the blocking voltage was 950V with gate shorted to the source.