Papers by Author: Sumi Krishnaswami

Abstract: The performance and characterization of SiC JFETs and BJTs, used as inverter switching devices, in a 2 kW, high temperature, 33 kHz, 270-28 V DC-DC converter has been accomplished. SiC and Si power devices were characterized in a phase shifted H-bridge converter topology utilizing novel high temperature powdered ferrite transformer material, high temperature ceramic filter capacitors, SiC rectifiers, and 10 oz. 220oC polyimide printed circuit boards. The SiC devices were observed to provide excellent static and dynamic characteristics at temperatures up to 300oC. SiC JFETs were seen to exhibit on-resistance trends consistent with temperature-mobility kinetics and temperature invariant dynamic loss characteristics. SiC BJTs exhibited positive temperature coefficients (TCE) of VCE and negative β TCEs, with only a 2-fold increase in on-resistance at 300oC. Both SiC power devices possessed fast inductive switching characteristics with τon and τoff ~100-150 ns when driving the transformer load. The SiC converter characteristics were compared to Si-MOSFET H-bridge operation, over its functional temperature range (30-230oC), and highlights the superiority of SiC device technology for extreme environment power applications.

Abstract: High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.

Abstract: Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.

Abstract: Gate oxide reliability measurements of 4H-SiC DMOSFETs were performed using the Time Dependent Dielectric Breakdown (TDDB) technique at 175°C. The oxide lifetime is then plotted as a function of the electric field. The results show the projected oxide lifetime to be > 100 years at an operating field of ~3 MV/cm. Device reliability of 2.0 kV DMOSFETs was studied by stressing the gate with a constant gate voltage of +15 V at a temperature of 175°C, and monitoring the forward I-V characteristics and threshold voltage for device stability. Our very first measurements show very little variation between the pre-stress and post-stress conditions up to 1000 hrs of operation at 175°C. In addition, forward on-current stressing of the MOSFETs show the devices to be stable up to 1000 hrs of operation.

Abstract: 8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.

Abstract: For the first time, 4H-SiC RF bipolar junction transistors have been used to produce an output power in excess of 2.1 kW at 425 MHz. For an input pulse width of 2 μs and 1% duty cycle, the power gain at peak output power is 6.3 dB with the collector efficiency and power added efficiency [PAE] being 45% and 35%, respectively, at a collector supply voltage of 75 V in a class C configuration. The package consists of 24 cells (2 chips) having an emitter periphery of approximately 1 inch per cell. Each cell produced a DC current gain (β) of 15 and a common emitter breakdown voltage (BVCEO) greater than 250 V. A peak output power of 87 W per cell was obtained at 425 MHz, as compared to the earlier report of 50 W per cell [1, 2] by using a shorter pulse width and duty cycle.

Abstract: SiC BJTs show instability in the I-V characteristics after as little as 15 minutes of operation. The current gain reduces, the on-resistance in saturation increases, and the slope of the output characteristics in the active region increases. This degradation in the I-V characteristics continues with many hours of operation. It is speculated that this phenomenon is caused by the growth of stacking faults from certain basal plane dislocations within the base layer of the SiC BJT. Stacking fault growth within the base layer is observed by light emission imaging. The energy for this expansion of the stacking fault comes from the electron-hole recombination in the forward biased base-emitter junction. This results in reduction of the effective minority carrier lifetime, increasing the electron-hole recombination in the base in the immediate vicinity of the stacking fault, leading to a reduction in the current gain. It should be noted that this explanation is only a suggestion with no conclusive proof at this stage.

Abstract: This paper reports on a 400 watt boost converter using a SiC BJT and a SiC MOSFET as the switch and a 6 Amp and a 50 Amp SiC Schottky diode as the output rectifier. The converter was operated at 100 kHz with an input voltage of 200 volts DC and an output voltage of 400 volts DC. The efficiency was tested with an output loaded from 50 watts to 400 watts at baseplate temperatures of 25°C, 100°C, 150°C and 200°C. The results show the converter in all cases capable of operating at temperatures beyond the range possible with silicon power devices. While the converter efficiency was excellent in all cases, the SiC MOSFET and 6 Amp Schottky diode had the highest efficiency. Since the losses in a boost converter are dominated by the switching losses and the switching losses of the SiC devices are unaffected by temperature, the efficiency of the converter was effectively unchanged as a function of temperature.

Abstract: We report on the development of the first 1 cm x 1 cm SiC Thyristor chip capable of blocking 5 kV. This demonstrates the present quality of the SiC substrate and epitaxial material. A forward drop of 4.1 V at 100 A and 25°C has been measured. The turn-on delay is found to be a strong function of the gate current. At a gate current of 0.5 A, a turn-on delay of 250 ns is observed for an anode to cathode current of 200 A. The turn-on delay reduces to 72 ns for an IG = 1.5 A. The turn-on rise time is a strong function of the anode to cathode voltage, VAK. At VAK =230 V, the turn-on rise-time is 300 ns for IAK =200 A. The rise-time reduces to 26 ns for VAK = 500 V.

Abstract: For 1-kV, 30-A 4H-SiC epitaxial emitter npn bipolar junction transistors, the dependence of the common-emitter current gain β on the collector current IC were measured at elevated temperatures. The collector-emitter voltage was fixed (at 100 V voltage) to provide an active operation mode at all collector currents varying in a wide range from 150 mA to 40 A (current densities 24 - 6350 A/cm2). The maximum room temperature current gain was measured to be βmax = 40 (IC = 7 A) while βmax = 32 (IC = 10 A) at 250oC. The β-IC dependences were simulated using a model which takes into account the main processes affecting the current gain. Minority carrier lifetimes and surface recombination velocity were obtained by means of those considerations.