Papers by Author: Yuichiro Nanen

Abstract: We evaluated the effect of NO annealing on hole trapping characteristic of SiC metal-oxide-semiconductor (MOS) capacitor by measuring flatband voltage (V_FB) shifts during a constant negative gate voltage stress under UV illumination. Under low stress voltages, the V_FB shift due to hole trapping was found to be suppressed by NO annealing. However, the V_FB shift of the NO-annealed device increases significantly with stress time under high stress voltage conditions, while the device without NO annealing showed only a slight shift. This result implies that NO annealing enhances generation of hole traps, leading to the degradation of SiC-MOS devices in long-term reliability.

Abstract: Characteristics of high-voltage lateral silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) with various reduced surface field (RESURF) structures were simulated. Breakdown voltage was enhanced from 5300 V for single-zone RESURF to 7400 V for two-zone, and to 7600 V for quasi-modulated RESURF MOSFETs.

Abstract: Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.

Abstract: The authors investigated the effect of preannealing on N-/Al-coimplanted and over-oxidized Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). The preannealing process causes a decrease of the Hall mobility and the effective mobility, and an increase of the interface state density. Secondary ion mass spectroscopy (SIMS) measurements revealed that the N concentration at the SiO2/SiC interface in preannealed samples is lower than in not-preannealed samples, which might be the reason for in the increase of the interface state density. In MOSFETs without preannealing, more N atoms are piled up at the SiO2/SiC interface, leading to the lower interface state density and higher mobility.

Abstract: Two electrical measurement techniques are frequently employed for the characteri- zation of traps at the SiO2/SiC interface: the thermal dielectric relaxation current (TDRC) and the conductance method (CM). When plotting Dit as a function of the energy position Eit in the bandgap both techniques reveal comparable results for deep interface traps (EC􀀀Eit > 0:3 eV). For shallower traps, CM always shows a strong increase of Dit which originates from near interface traps (NIT). TDRC provides a contradictory result, namely a slight decrease of Dit. In this paper, we show that the position of NITs in the oxide close to the interface is responsible for the invisibility of these traps in TDRC spectra. We further show that NITs become detectable by the TDRC method by using a discharging voltage Vdis close to the accumulation regime. However, due to the Shockley-Ramo-Theorem the contribution of NITs to the Dit in TDRC spectra is strongly suppressed and can be increased by using thin oxides.

Abstract: 4H-SiC (0001) MOSFETs with a three-dimensional gate structure, which has a top channel on the (0001) face and side-wall channels on the {11-20} face have been fabricated. The three-dimensional gate structures with a 1-5 m width and 0.8 m height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300°C. The fabricated MOSFETs have exhibited superior characteristics: ION / IOFF, the subthreshold swing and VTH are 1010, 250 mV/decade and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1 m-wide MOSFET is ten times higher than that of a conventional planar MOSFET.