Papers by Keyword: Gate Dielectric

Abstract: The paper presents some results on the effect of the metal electrode deposition on the electrical performance of amorphous polymthylmetacrylate (PMMA) thin films, measured in a MIM structure consisting of metal (Al)-insulator (PMMA)-metal (Ta). Aluminium (Al) electrode was deposited by physical vapor deposition method (PVD) on the top of PMMA film with the deposition rate of 5 and 10Å/s. The effect of aluminium deposition rate and post deposition annealing temperature on the morphology of the interface between Al electrode (100 or 300 nm thick) and PMMA thin film (40 or 70 nm thick) has been investigated by cross-section scanning electron microscopy (SEM). Based on SEM data, I-V characteristic measurements and dielectric constant values of insulating films, the deposition parameters of Al top-electrode was optimised. Our results showed that when the deposition of the Al electrode take place at a rate of 10 Å/s, no inter-diffusion or interfacial reaction at the interface between Al electrode and PMMA films were observed and the best delectric parameters of PMMA thin film were measured, which led to the best dielectric performance of PMMA layer in TFT configuration.

Abstract: We present the influence of phosphorous auto-doping on the characteristics of the oxide interface in 4H-SiC following high temperature gate oxide annealing. IV characteristics show no evidence of direct tunnelling breakdown; however Fowler Nordheim (F-N) conduction is observed in high electric field with the oxides able to sustain >10MV/cm. Capacitance Voltage data show D_IT <1x10¹² eV^-1cm^-2 close to the conduction band edge after POA, with undoped samples demonstrating D_IT below 5x10¹¹ eV^-1cm^-2. Photo CV data indicates smaller flat band voltage shifts of 0.6V at midpoint for the undoped samples, in comparison to 0.9V for the phosphorous doped devices. Temperature and bias stress tests at 200°C showed marginal hysteresis (0.3V) in both wafers. Reliability of time-dependent constant current and constant voltage characteristics revealed higher TDDB lifetimes in the undoped wafer. We conclude that the unintentional incorporation of phosphorous into the gate stack as a result of high temperature POA of the doped field oxide leads to a variation in flat band shift, higher D_IT, and lower dielectric reliability.

Abstract: ZrO₂ films were deposited on C-face 4H-SiC substrates by using an RF sputter at a temperature of 200°C. Then, ZrO₂ films were treated with RTA (rapid thermal annealing) process in Argon (Ar) ambient at 600°C, 700°C and 800°C for 4 minutes, respectively. The samples with RTA process show the lower leakage currents. As the measure temperature increases from room temperature (RT) to 150°C, the dielectric breakdown voltage reduces from 3 V to 1 V. The difference between quasi C-V characteristics and high frequency C-V characteristics at 1 MHz becomes larger with increasing RTA temperature. The C-V curves also shift to the left side as the measure temperature increases from RT to 150°C. It also shows the ledge on the C-V curves of samples with RTA at elevated measure temperature.

Abstract: We demonstrated the impact of plasma nitridation on thermally grown GeO2 for the purposes of obtaining high-quality germanium oxynitride (GeON) gate dielectrics. Physical characterizations revealed the formation of a nitrogen-rich surface layer on the ultrathin oxide, while keeping an abrupt GeO2/Ge interface without a transition layer. The thermal stability of the GeON layer was significantly improved over that of the pure oxide. We also found that although the GeO2 layer is vulnerable to air exposure, a nitrogen-rich layer suppresses electrical degradation and provides excellent insulating properties. Consequently, we were able to obtain Ge-MOS capacitors with GeON dielectrics of an equivalent oxide thickness (EOT) as small as 1.7 nm. Minimum interface state density (Dit) values of GeON/Ge structures, i.e., as low as 3 x 1011 cm-2eV-1, were successfully obtained for both the lower and upper halves of the bandgap.

Abstract: It was experimentally shown that an ONO gate dielectric carefully formed on 4H-SiC has extremely high reliability even under a negative electric field at least up to a junction temperature of 300°C, making it promising for power MOS and CMOS applications. Medium charge to failure of –30 C/cm2 was achieved for fully processed polycrystalline Si gate MONOS capacitors with an equivalent SiO2 thickness of teq = 44 nm and a 200-μm diameter. The medium time to failure of these capacitors projected for –3 MV/cm exceeds 86 and 6.3 thousand years at room temperature and 300°C, respectively. A parasitic memory action did not appear even when Eox of -6.6 MV/cm was applied for 5000 seconds.

Abstract: In this work we present a comprehensive comparison of ultra thin thermally nitrided (TN) to plasma nitrided (PN) gate dielectrics (GD). We will show that thermal nitridation is a promising technique to increase the nitrogen concentration up to 25%. Furthermore, we will demonstrate that ultra thin thermally nitrided GD have the potential to be an alternative solution compared to plasma nitrided GD. This work includes the analysis of physical and electrical parameters as well as reliability results from reliability characterization. Additionally, we investigated the impact of Deuterium on electrical parameters and reliability behavior.

Abstract: In this paper, gate dielectric scaling with nitrogen incorporation technologies is reviewed. In key technologies such as thermal nitridation, oxide/nitride stacked dielectric structure and nitrogen implant/plasma played fundamental role in advance of semiconductor industry. Besides the technologies, primary integration schemes and their impacts on device performance and reliability are also covered.