Papers by Keyword: Interface States (or Traps)

Abstract: We studied the annealing process to improve the field-effect channel mobility (μFE) on the 4H-SiC (11-20) face. We found that wet annealing, in which a wet atmosphere was maintained during the cooling-down period to 600°C after wet oxidation, was effective. The interface states (Dit) near the conduction band edge decreased and the μFE increased up to 244 cm2/Vs. Furthermore, the origin of this high channel mobility was investigated using secondary ion mass spectroscopy (SIMS) measurement and thermal desorption spectroscopy (TDS) analysis. It was indicated that the hydrogen density at the MOS interface was increased by the wet annealing and the hydrogen was desorbed mainly at temperatures between 800 °C and 900 °C. These hydrogen desorption temperatures also corresponded to the temperatures of the μFE reduction by argon annealing after the wet annealing. These results indicated that this high channel mobility was achieved by hydrogen passivation during the wet annealing at temperatures between 800 °C and 900 °C.

Abstract: The improvement of the SiC-SiO2 interface has been the main focus of research in SiC MOSFET technology due to the presence of high density of interface traps (Dit) leading to poor threshold voltage temperature stability and poor mobility. In SiC MOSFETs with the gate oxide grown in the presence of sodium, known as sodium enhanced oxidation(SEO), a lower Dit and higher field effect mobility has been observed [1]. Hall effect measurements were performed from 125°K-225°K on such MOSFET samples. The Hall measurements were made as a function of temperature for various sheet charge concentrations. The sheet charge density was measured as a function of gate bias at 225°K and there is very little trapped charge in the sample with oxide grown by SEO while about 50 % of the total charge is trapped in a sample with N2O grown oxide annealed in NO. In samples with oxide grown by SEO, there is a monotonic increase in mobility with sheet charge density and the mobility also increases with temperature. This is an indication that the main scattering mechanism is Coulomb scattering in this regime.

Abstract: Deposited SiN/SiO2 stack gate structures have been investigated to improve the 4H-SiC MOS interface quality. Capacitance-voltage measurements on fabricated SiN/SiO2 stack gate MIS capacitors have indicated that the interface state density is reduced by post-deposition annealing in N2O at 1300°C. The usage of thin SiN and increase in N2O-annealing time lead to a low interface state density of 1×1011 cm-2eV-1 at EC – 0.2 eV. Oxidation of the SiN during N2O annealing has resulted in improvement of SiC MIS interface. The fabricated SiN/SiO2 stack gate MISFETs demonstrate a high channel mobility of 32 cm2/Vs on (0001)Si face and 40 cm2/Vs on (000-1)C face.

Abstract: This paper describes a series of electrical measurements and sample modifications that enabled the electrical properties of hybrid-orientation direct silicon bonded wafer interfaces to be determined. It is shown that the carrier transport across this near-surface (110)Si/(100)Si boundary is dictated by the defects present at the bond interface. These interface states are believed to pin the Fermi-level, producing a conduction barrier with a thermal activation energy Ea = 0.56eV. The defect band has been identified by deep-level transient spectroscopy and associated with the defect states typically observed in plastically deformed silicon. The carrier transport behavior across the bonding interface, as well as the observed interface trap levels are therefore attributed to the dislocation network present at the bonding interface. The spatial uniformity of the interface properties have been evaluated by TEM, electron-beam induced current microscopy, photoconductive decay and conduction measurements.

Abstract: SiC MOSFETs have very large interface trap densities which degrade device performance. The effect of traps on inversion layer mobility and inversion charge concentration has been studied, and mobility models suitable for inclusion in Drift-Diffusion simulators have been developed for steady state operation of SiC MOSFET devices. Here, we attempt to model the transient behavior of SiC MOSFETs, and at the same time, extract the time constants for the filling and emptying of interface traps. As compared to the inversion layer, interface traps in SiC MOSFETs are slow in reacting to change in gate bias. So, at the positive edge of a gate pulse, we see a large current in the MOSFET, which then decays slowly to the steady state value as the interface traps fill up. We have developed a generation/recombination model for minority carriers in a SiC MOSFET based on the Shockley-Read-Hall recombination model for electrons and holes. In our model, the generation/recombination takes place between minority carriers in the inversion layer, and the traps at the SiC-SiO2 interface. Comparing our simulated current vs. time curves to experiment, we have been able to extract time constants for the filling and emptying of traps at the SiC-SiO2 interface.

Abstract: In prior work we have proposed a mobility model for describing the mobility degradation observed in SiC MOSFET devices, suitable for being implemented into a commercial simulator, including Coulomb scattering effects at interface traps. In this paper, the effect of temperature and doping on the channel mobility has been modelled. The computation results suggest that the Coulomb scattering at charged interface traps is the dominant degradation mechanism. Simulations also show that a temperature increase implies an improvement in field-effect mobility since the inversion channel concentration increases and the trapped charge is reduced due to bandgap narrowing. In contrast, increasing the substrate impurity concentration further degrades the fieldeffect mobility since the inversion charge concentration decreases for a given gate bias. We have good agreement between the computational results and experimental mobility measurements.

Abstract: In this paper we give a comparative study of two types of gate oxidation of n-channel 6HSiC MOSFETs. One set of transistors was fabricated using pyrogenic oxidation with no postoxidation annealing, and for the second set the oxide was grown in dry O2 with post-oxidation annealing. The lateral MOSFETs show a Hall mobility of ~ 75 cm2/Vs which is essentially same for both types of oxide. From the IV characteristics curves, the latter devices exhibit an average effective channel mobility of 72 (± 5) cm2/Vs, whereas the former has a value of 30 (± 3) cm2/Vs. From the capacitance and conductance measurements, the interface trap density for pyrogenicgrown oxide using is roughly a factor of 2 greater than those grown by dry oxidation. We found that the pyrogenic post-oxidation anneal at 1073K helps to reduce the interface states density and improves the effective channel mobility of 6H-SiC MOSFETs.

Abstract: It is of great importance to investigate the electrical properties of SiC p-channel MOSFETs for development of SiC CMOS technology. In the present report, we investigated dependences of electrical properties of the SiC p-channel MOSFETs on SiC poly-types. The on-state characteristics (channel mobility, threshold voltage, and temperature dependences) for the 4H- and 6H-SiC p-channel MOSFETs showed similar behavior, although those of 4H-SiC n-channel MOSFETs are usually quite different from those of 6H-SiC. These results might be caused by the similar SiC MOS interface state distribution around the valence band edge.

Abstract: We performed high-pressure H2O vapor annealing on 4H-SiC n-MOS capacitors to control SiO2/4H-SiC interface properties. High-pressure H2O annealing was performed at 270～ 420oC at a pressure of 1.31～1.67MPa. Effective negative fixed oxide charge decreased with increasing anneal temperature in the case annealed with Al gate electrodes. However, it increased with increasing anneal temperature in the case annealed without Al gate electrodes. The effect of annealing was much larger on the C-face than that of Si-face. Interface state densities near the conduction band edge was decreased at 420oC under 1.67MPa compared to other samples, especially on the C-face n-MOS capacitors.

Abstract: In this study, we have investigated N2O oxidation of various off-angled 4H-SiC (0001) epilayers and characterized the properties of MOS interfaces. The oxide thickness almost linearly increases with increasing off-angle. Oxidation on highly off-angled (0001) 4H-SiC is faster than that on 8o off-axis (0001). The off-angle dependence of Dit is very small for the MOS capacitors in the off-angle range from 8o to 30o. The depth profiles of carbon and nitrogen atoms near the MOS interface on 15o off-axis 4H-SiC(0001) are similar to those on 8o off-axis (0001).