Papers by Keyword: MESFET

Abstract: Lateral gate depletion expansion towards drain contact has been analyzed on p-type diamond metal-semiconductor field effect transistor by electron beam induced current. The investigation was restricted to a closed channel to simplify the study and to directly observe the expansion of the lateral depletion region. The experimental data agreed with the theoretical model given in the literature.

Abstract: The 4H-SiC ultraviolet detector of the MESFET structure with gain is proposed and simulated in this paper. The Schottky gate of MESFET is transparent or semi-transparent to allow more of the incident UV light to be absorbed in the device. The effect of the doping and thickness of the channel layer on the photocurrent of the 4H-SiC MESFET UV detector is simulated and the effect mechanism is analyzed. The simulation results show that the 4H-SiC MESFET exhibits photocurrent below 380 nm. And only when the channel of the 4H-SiC MESFET is in the open state there will be a gain in the detector. Shorter gate length is beneficial to improve the responsivity and the gain of the 4H-SiC MESFET UV detector. When the gate length is set to 10 μm with the channel thickness of 0.3 μm and channel doping of 1×10¹⁷ cm^-3, the peak responsivity and the gain are calculated to be 12.9 A/W and 55.6 respectively.

Abstract: Due to our demonstrated stable Tungsten-Schottky barrier at elevated temperatures, and also thanks to our technological process maturity regarding SiC-Schottky contact fabrication, we have implemented the digital logic gates library adopting a normally-on MESFET topology. In this paper we present new experimental results showing the thermal behavior up to 300oC of 4H-SiC logic gates library, monolithically integrating normally-on MESFETs and epitaxial resistors. The implemented SiC devices are based on important CMOS features and are specially designed for large ICs device integration density.

Abstract: An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco^®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Abstract: The design and development of SiC integrated circuits (ICs) nowadays is a necessity due to the increasing demand for high temperature intelligent power applications and intelligent sensors. Due to the superior electrical, mechanical and chemical proprieties of 4H-SiC poly-type, 4H-SiC MESFET transistor is a good compromise for ICs on SiC able to work at higher temperatures (HT) than on Si. This paper presents new experimental results of approaching embedded logic gates with SiC MESFETs and resistors, built in junction-isolated tubs. The P+ implantation isolation technology offers important perspectives regarding the integration density of devices per unit area and wafer surface, being able to use far more complex design geometry for modeling ICs on SiC.

Abstract: A novel 4H-SiC MESFET with stepped-channel (stepped-spacer) structure is proposed for the first time and analyzed by 2D numerical simulation. Based on the stepped buried oxide structure of SOI which can produce additional electrical Electric field peaks, much more advantages can be obtained through a stepped-channel structure compared to that of the field terminal technology, such as an obvious increase of the breakdown voltage which is equal to the electric field to the path integral, and the lower capacitances lead to a higher cut-off frequency. The simulation results show that a 100% higher saturated drain current and a 153% larger breakdown voltage can be obtained utilizing the stepped-channel structure MESFET than those of the conventional counterpart.

Abstract: An experimental investigation has been carried out with clarifying the external mechanical stress effect on GaAs metal-semiconductor field-effect transistor (MESFET) I-V characteristic curve which as the sensitive element of micro-accelerometer in different condition. In this paper, we research different channel directions to explore the output characteristics of the GaAs MESFET which fabricated at the root of the cantilever. We design three channel directions which angled with the cantilever as 0 degree, 45 degree, 90 degree. We find that when the Channel direction parallel to the cantilever direction, ∆U has the maximum value of 12.13mv. The sensitivity of 0 degree is 0.04mv/g higher than the 90 degree. The dynamic result indicates that the channel direction parallel to the cantilever direction is the optimized design structure.

Abstract: SiC MESFETs were scaled both laterally and vertically to optimize high frequency and high power performance. Two types of epi-stacks of SiC MESFETs were fabricated and measured. The first type has a doping of 3×1017 cm-3 in the channel and the second type has higher doping (5×1017 cm-3) in the channel. The higher doping allows the channel to be thinner for the same current density and therefore a reduction of the aspect ratio is possible. This could impede short channel effects. For the material with higher channel doping the maximum transconductance is 58 mS/mm. The maximum current gain frequency, fT, and maximum frequency of oscillation, fmax, is 9.8 GHz and 23.9 GHz, and 12.4 GHz and 28.2 GHz for the MESFET with lower doped channel and higher doping, respectively.

Abstract: Some new techniques include n- shielding, buried channel and field plate are firstly adopted together for design and fabrication of 4H-SiC microwave MESFETs. The testing results show that a relatively broad and uniform transconductance versus gate voltage was obtained using a 0.1m n- shielding. 0.3mm gate periphery device shows good DC and RF performance such as 5.27W/mm power density, 6.7dB power gain and 43% power added efficiency at 2.3GHz under pulse operation. Compared to conventional SiC MESFETs, a gate lag ratio as high as 0.84 can be achieved for the developed devices even under a nearly actual operating condition.

Abstract: Lateral normally-on dual gates MESFETs withstanding a drain/source voltage in excess of 200V have been fabricated on semi-insulating 4H-SiC substrate. This paper reports on the fabrication, DC characterization and in-circuit behavior of the MESFETs. Temperature dependent DC characterization has been carried out up to 473K. The performances of basic analog circuits such as an amplifier and a clock, using these MESFETs, are detailed and analyzed.