Papers by Keyword: Mesa

Abstract: 10 kV class 4H-SiC bipolar diodes have been fabricated. Two different edge terminations (Mesa/JTE or MESA/JTE with JTE rings) with two different junction bend radius have been designed and tested. Measurement results show that the inclusion of JTE rings improve the edge termination efficiency. The measurements indicate also a better reverse performance of diodes with larger bend radius.

Abstract: The sloped sidewall angle in 4H-SiC mesa structure could be controlled by a thermal etching at 900oC in chlorine (Cl2) based ambience. 4H-SiC C face with 8o off substrate was used. The SiO2 layers for the etching mask were formed by a deposited SiO2 layer or a thermally oxidized layer. Thermal etching was carried out at Cl2 ambience at 900oC for 15 minutes. The surface morphologies of the mesa structures were observed with the scanning electron microscope (SEM) and atomic force microscope (AFM). The sloped angles at the mesa sidewalls using deposited SiO2 mask and thermal SiO2 mask were about 23o and 60o, respectively. These results mean that the angle of sloped sidewall can change by mask fabrication method.

Abstract: In this work we report on 3C-SiC heteroepitaxial growth on 4H-SiC(0001) substrates which were patterned to form mesa structures. Two different deposition techniques were used and compared: vapour-liquid-solid (VLS) mechanism and chemical vapour deposition (CVD). The results in terms of surface morphology evolution and the polytype formation using these growth techniques were studied and compared. It was observed both 4H lateral growth from the mesa sidewalls and 3C enlargement on top of the mesas, the former being faster with CVD and VLS. Only VLS technique allowed elimination of twin boundaries for proper orientation of the mesa sidewalls.

Abstract: We report on new observations made, when 4H-SiC, Si-face substrate mesas, having either low tilt-angle (< 1°) with steps or step-free top surfaces, were exposed to three separate HCl etching conditions for five minutes at temperatures of 1130°C, 1240°C and 1390°C. We observed that HCl was ineffective at 1130°C, as etching was incomplete with abundant surface contamination. At 1240°C, screw dislocations were aggressively etched by HCl, while multiple shallow flat-bottomed etch pits were formed on step-free mesa surfaces. At 1390°C, step-flow etching dominated as large etch pits were formed at screw dislocations and previously step-free surfaces etched inward from mesa edges to form parallel rows of organized steps.

Abstract: This paper presents a comparison of the reverse characteristics of mesa terminated PiN diodes fabricated on n- and p-type 4H-SiC substrates. For n-type the attained breakdown voltages are higher and for p-type lower than expected. This is likely to be explained by the presence of negative charges at the interface between passivation oxide and SiC. Supported by XPS data we come to the conclusion that the RIE process creates surface charges which have an impact on the breakdown voltage of the fabricated diodes.

Abstract: Sloped sidewalls in 4H-SiC mesa structures on the (000-1) C face were formed by a Cl2-O2 thermal etching method. The etching rate of 4H-SiC (000-1) C face was 10 times faster than that of (0001) Si face, and the etching rate at 910oC was about 18μm/h. The etched surface was rather smooth, and the sidewall of the mesa was inclined to the off-axis substrate. Taking into account the off angle of about 8o toward [11-20] off direction, the angles of the sidewalls were 52-56o for the <1-100> and 55-57o for the <11-20> directions from the crystallographically accurate (000-1) C face. Epitaxial pn junction diodes with the sloped sidewalls structure were fabricated, which had good electrical properties.

Abstract: The lateral expansion of thin homoepitaxial cantilevers from mesas has been used to produce areas of on-axis 4H-SiC completely free of dislocations. Cantilever expansion is influenced by the geometric shape and crystallographic orientation of the pregrowth mesa. In order to form larger areas of defect free silicon carbide (SiC), progressive coalescence must occur when adjoining cantilevers merge. The progressive coalescence is largely dictated by the shape and orientation of the pregrowth mesa. We report on refinements to the pregrowth mesa geometry and orientation that allows rapid initiation of cantilever growth and promotes progressive coalescence of merging cantilevers. These modifications to the pregrowth mesa geometry permit larger areas of defect free 4H-SiC to be realized.

Abstract: This paper reports on initial fabrication and electrical characterization of 3C-SiC p+n junction diodes grown on step-free 4H-SiC mesas. Diodes with n-blocking-layer doping ranging from ~ 2 x 1016 cm-3 to ~ 5 x 1017 cm-3 were fabricated and tested. No optimization of junction edge termination or ohmic contacts was employed. Room temperature reverse characteristics of the best devices show excellent low-leakage behavior, below previous 3C-SiC devices produced by other growth techniques, until the onset of a sharp breakdown knee. The resulting estimated breakdown field of 3C-SiC is at least twice the breakdown field of silicon, but is only around half the breakdown field of <0001> 4H-SiC for the doping range studied. Initial high current stressing of 3C diodes at 100 A/cm2 for more than 20 hours resulted in less than 50 mV change in ~ 3 V forward voltage.

Abstract: Cross-sectional transmission electron microscopy (TEM) was used to investigate the extended defects in 3C-SiC films deposited on atomically flat 4H-SiC mesas. The nominal layer thickness was 10 μm and was considerably larger than the critical thickness determined by either the Matthews and Blakeslee or People and Bean models. Threading dislocation densities determined by KOH etching are far below densities typical of relaxed heteroepitaxial layers, down to as low as 104cm-2 densities found in 4H-SiC. Misfit dislocations with Burgers vectors of <11 2 0> were observed in planes parallel to the 3C/4H SiC interface. These defects were interpreted as due to nucleation of dislocation half loops at mesa edges and glide along the 3C/4H interface.

Abstract: Overcoming the physical limits of silicon, silicon carbide shows a high potential for making high voltage thyristors. After a simulation based optimization of the main thyristor parameters, including JTE protection and a SiO2 layer passivation, 4H-SiC GTO thyristors were realized and characterized. Designed for a theoretical blocking capability of nearly 6 kV, the electrical characterization of all device structures revealed a maximum blocking voltage of 3.5 kV. Comparing simulation and measurement suggests that a negative oxide charge density of ~ 2×1012 cm-2 causes the decrease in electrical strength.