Papers by Keyword: Minority Carriers

Abstract: We address the key factors limiting charge carrier lifetime in 4H-SiC epilayers by demonstrating a viable method for eliminating carbon vacancy (V_C) related Z_1/2 lifetime killer sites and by introducing a novel approach in depth-resolved characterization of the carrier lifetimes across the epitaxial layer, which allows monitoring the efficacy of the proposed defect reduction scheme also exposing surface and interface recombination effects. We show that a moderate-temperature annealing conducted at 1500 °C for 6 hours under C-rich thermodynamic equilibrium conditions in effect eliminates carbon vacancies in epilayers to the levels below the detection limit (10¹¹ cm^-3) of DLTS measurements. The efficient reduction of V_C-related Z_1/2 sites upon thermal treatment is further proven by a significant increase of the minority carrier lifetime from 0.3µs to 1 µs, the upper limit apparently set by epilayer thickness dependent lifetime. Equally important is the extensive range of defect elimination as evidenced by consistently enhanced lifetime throughout entire 40 μm-thick epilayer, thus suggesting immediate practical implication as a lifetime control method suitable for variable thickness 4H-SiC epilayers.

Abstract: Lifetime maps for two 4H-SiC epi-wafers (samples 1 and 2) were recorded using microwave photoconductive decay (μPCD) measurements and correlated with the type and distribution of structural defects mapped by synchrotron X-ray topography (white beam and monochromatic). Sample 1 showed lower lifetime inside one of its higher doped facet regions and along its edges. The low lifetime in the facet region was associated with the presence of a high density of multi-layered Shockley stacking faults (SFs) and low angle grain boundaries (LAGBs). These stacking faults are likely double Shockley stacking faults (DSSFs) and probably nucleated from scratches present on the substrate surface and LAGBs present in that region, propagating during epilayer growth. In contrast, sample 2 showed a reduced carrier lifetime in the middle region associated with a network of interfacial dislocations (IDs) and half loop arrays (HLAs) originating from 3C inclusions that are generated during epilayer growth. Along the edges of both samples, overlapping triangular defects, microcracks and BPD loops lowered lifetime.