Papers by Keyword: Near Interface Traps

Abstract: The reliability issue of threshold voltage (V_gs(th)) still exists in Silicon carbide (SiC) based metal-oxide-semiconductor-field-effect-transistors (MOSFETs). In this paper, the threshold voltage instability of 4H-SiC MOSFET is deeply studied through Silvaco TCAD simulation. This work mainly investigates the instability (shift) of the V_gs(th) affected by interface states (interface traps), near interface traps, and mobile ions. The results display that the effect of near interface traps on the V_gs(th) shift is greater than that of interface traps. The electron capture ability is related to the energy level of the traps. With the energy level increasing, the V_gs(th) shift increases firstly and then decreases. The peak energy level is related to the trap position and trap density. Furthermore, the effect of the mobile ions in the oxide layer on the V_gs(th) shift is limited. However, when moving to the SiC/SiO₂ interface, they will greatly impact the V_gs(th) and affect the device performance seriously.

Abstract: In this paper, near interface traps (NITs) in lateral 4H-SiC MOSFETs were investigated employing temperature dependent transient gate capacitance measurements (C-t). The C-t measurements as a function of temperature indicated that the effective NITs discharge time is temperature independent and electrons from NITs are emitted toward the semiconductor via-tunnelling and/or trap-to-trap tunnelling. The NITs discharge time was modelled taking into account also the interface state density in a distributed circuit and it allowed to locate traps within a distance of about 1.3nm from the SiO₂/4H-SiC interface.

Abstract: Current power MOSFET devices on Silicon Carbide show a limited inversion channel mobility, which can be a result of the expected very high density of interface states near the conduction band . In the current work, the effect of the post implantation annealing temperature, the thermal oxidation and the nitrogen doping of the n-epi layer on the density of these interface traps is investigated using capacity-conductance measurements. Instead of the usage of very high frequencies as used in , in this investigation the measurements were performed in liquid nitrogen to decrease the recharging times of the interface traps.Due to the different processing the samples showed a wide spreading of the inversion channel mobility. The conductance measurements show a characteristic peak caused by the conduction band near interface traps especially for the low temperature measurements. But these traps could not be correlated to the mobility. Instead, a correlation to the nitrogen doping of the epi layer could be observed.

Abstract: In an attempt to significantly reduce the amount of nitric oxide (NO), commonly used to improve the quality of gate oxides on 4H–SiC, a series of alternative gate oxidation processes using a combination of O₂ and NO gas mixtures at low partial pressures were investigated. The properties of 4H–SiC/SiO₂ interfaces on n-type MOS capacitors were examined by the measurement of accumulation conductances over a range of frequencies. Oxide integrity was evaluated by current–voltage measurements and by the extraction of the conduction band offset barrier heights through Fowler–Nordheim (F–N) analysis. A notable reduction of accumulation conductance, indicating a reduction of near-interface traps (NITs), was observed over all measured frequencies for oxidation processes containing NO with a partial-pressure of only 2%. Gate oxides grown in mixture of O₂ and NO at low-partial-pressures demonstrated a considerable improvement of dielectric properties, increasing the barrier height to near theoretical values.

Abstract: Instability of metal-oxide-semiconductor field-effect transistor (MOSFET) characteristics was evaluated by DC and pulse current-voltage (I-V) measurements. MOSFETs with nirided gate oxides were fabricated on C-face 4H-SiC. Their interfaces have near interface traps (NITs) with long time constants, depending on the cooling down process after nitridation. Such devices exhibited a large hysteresis in DC I-V and a large transient current in pulse I-V measurements. These phenomena can be explained by the charge state of NITs due to capture/emission of electrons in the channel.

Abstract: Characteristics of metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated by direct oxidation of C-face 4H-SiC in NO were investigated. It was found that nitridation of the C-face 4H-SiC MOS interface generates near-interface traps (NITs) in the oxide. These traps capture channel mobile electrons and degrade the performance of MOSFETs. The NITs can be reduced by unloading the samples at room temperature after oxidation. It is important to reduce not only the interface states but also the NITs to fabricate high-performance C-face 4H-SiC MOSFETs with nitrided gate oxide.

Abstract: Two electrical measurement techniques are frequently employed for the characteri- zation of traps at the SiO2/SiC interface: the thermal dielectric relaxation current (TDRC) and the conductance method (CM). When plotting Dit as a function of the energy position Eit in the bandgap both techniques reveal comparable results for deep interface traps (EC􀀀Eit > 0:3 eV). For shallower traps, CM always shows a strong increase of Dit which originates from near interface traps (NIT). TDRC provides a contradictory result, namely a slight decrease of Dit. In this paper, we show that the position of NITs in the oxide close to the interface is responsible for the invisibility of these traps in TDRC spectra. We further show that NITs become detectable by the TDRC method by using a discharging voltage Vdis close to the accumulation regime. However, due to the Shockley-Ramo-Theorem the contribution of NITs to the Dit in TDRC spectra is strongly suppressed and can be increased by using thin oxides.

Abstract: High-resolution transmission electron microscopy (HR TEM) reveals an atomically flat SiC surface after oxidation in either NO or dry O2 ambients. This reopens the question of the origin of the electronically active defects at the SiO2–SiC interface, whose density remains orders of magnitude higher than in the SiO2–Si interface. Capacitance-transient measurements, analysed in this paper, demonstrate that the dominant electronically active defects are in the oxide at tunneling distances from the SiC surface (near-interface traps). The HR TEM results cannot rule out that these traps are related to carbon/oxygen bonds or even nanometer-sized carbon clusters, which resolves the apparent inconsistency with the earlier experimental evidence of carbon accumulation at (or near) the SiO2–SiC interface.

Abstract: The density of interface traps (Dit) in thermally oxidized SiC is unacceptably high for MOS device fabrication. The most severe problem is posed by the extremely high concentration of slow acceptor states near the conduction band edge of 4H-SiC. These states are attributed to near interface traps originating from (probably intrinsic) defects in the oxide. Here a systematic theoretical search is presented for possible defects in the oxide with an appropriate acceptor level. Supercell calculations using a hybrid functional approach (and resulting in a correct gap) on defects in alpha-quartz exclude the oxygen vacancy and the oxygen interstitial, as possible candidates. In contrast, these calculations predict interstitial silicon to have an acceptor level in the appropriate range. The carbon interstitial in silica has an acceptor level somewhat deeper than that. Occupation of these levels give rise to significant rearrangement of the environment, leading to a more extended defect structure.