Papers by Keyword: P-N Junction

Abstract: A new technique that reduces stacking fault (SF) density in 3C-SiC, termed switch-back epitaxy (SBE), is demonstrated regarding its effects on morphological and electrical properties. SBE is a homoepitaxial growth process on backside of 3C-SiC grown on undulant-Si. The key feature of SBE, the surface polarity of residual SFs in 3C-SiC, which cannot be erased by heteroepitaxial growth on undulant-Si, is converted from the Si-face to the C-face. The SF density on the surface of 3C-SiC grown by SBE shows a remarkable decrease to one-seventh lower than that on undulant- Si. The leakage current of pn-diode epitaxially fabricated on the 3C-SiC substrate grown by SBE decreases to as low as one-thirtieth that on 3C-SiC substrate grown without SBE. These results suggest that SBE eliminates the SFs on the surface of 3C-SiC and subsequently reduces the leakage current at pn-junction thus fabricated.

Abstract: The electrical activity of threading dislocations (TDs), occurring in a thin SiGe Strain Relaxed Buffer (SRB) layer has been investigated by a number of techniques and its impact on the reverse current of p-n junction diodes has been evaluated. It is shown that besides the density of TD, there are at least two other parameters playing an important role. The distance with respect to the metallurgical junction of the 5 nm C-rich layer, used for the strain relaxation and the dopant type in the well region also affect the leakage current. This complex behaviour is further reflected in the Emission Microscopy (EMMI) images, showing different breakdown sites for p+/n or n+/p junctions. Results will be presented whereby one of these parameters is varied, while the others are kept constant, in order to arrive at some idea of the relative importance of the different factors.