Papers by Keyword: Post Implantation Annealing

Abstract: Van der Pauw devices have been fabricated by double ion implantation processes, namely P⁺ and Al⁺ co-implantation. Similarly to the source area in a SiC VD-MOSFET, a 5 × 10¹⁸ cm^-3 P plateau is formed on the top of a buried 3 × 10¹⁸ cm^-3 Al distribution for electrical isolation from the n- epilayer. The post implantation annealing temperature was 1600 °C. Annealing times equal to 30 min and 300 min have been compared. The increase of the annealing time produces both an increase of electron density as well as electron mobility. For comparison a HPSI 4H-SiC wafer, 1×10²⁰ cm^-3 P⁺ ion implanted and 1700 °C annealed for 30 min was also characterized.

Abstract: The results of the first experiments for achieving the thermal equilibrium during 1300 °C annealing of 1×10²⁰ cm^-3 ion implanted Al⁺ in 3C-SiC are shown. X-ray diffraction, through reciprocal space maps and 2Θ scans, characterizes the 3C-SiC lattice recovery. The achievement of a ohmic behavior of Ni/Al/Ti alloy indicates the onset of a measurable electrical activation of the Al implanted layer. The Al electrical activation is qualified through the implanted layer sheet resistance.

Abstract: A vertical 4H-SiC p-i-n diode with 2×10²⁰cm^-3 Al⁺ implanted emitter and 1950°C/5min post implantation annealing has been characterized by deep level transient spectroscopy (DLTS). Majority (electron) and minority (hole) carrier traps have been found. Electron traps with a homogeneous depth profile, are positioned at 0.16, 0.67 and 1.5 eV below the minimum edge of the conduction band, and have 3×10^-15, 1.7×10¹⁴, and 1.8×10^-14 cm² capture cross section, respectively. A hole trap decreasing in intensity with decreasing pulse voltage occurs at 0.35 eV above the maximum edge of the valence band with 1×10¹³ cm² apparent capture cross section. The highest density is observed for the refractory 0.67 eV electron trap that is due to the double negative acceptor states of the carbon vacancy.

Abstract: This study shows that, after annealing at 1950°C, a 1×10²⁰ cm^-3 Al⁺ implanted 4H-SiC material shows a decreasing resistivity with increasing annealing time in the range 5-25 min. After this, the resistivity remains constant up to an annealing time of 40 min. The estimated minimum time to gain the thermal equilibrium in this implanted material at 1950°C is 12 min. Electrical characterization has been performed in the 20-680 K temperature range.

Abstract: An inductively heated furnace and an ultra-fast microwave heating system have been used for performing post implantation annealing processes of P+ implanted semi-insulating <0001> 4H SiC at 1800-1950°C for 5 min and 2000-2050°C for 30 s, respectively. Very high P+ implantation fluences in the range 71019 81020 cm-3 have been studied. The annealing processes in the inductive furnace and the one at the lower temperature in the microwave furnace show a saturation in the efficiency of the electrical activation of the implanted P+ that is bypassed by the microwave annealing process at the higher temperature. The measured electron mobility values versus electron density are elevated in all the studied samples and for every post implantation annealing process. This has been ascribed to an elevated implanted crystal recovery due to the very high annealing temperatures > 1800°C.

Abstract: 6H and 4H–SiC epilayers were Al-implanted at room temperature with multiple energies (ranging from 25 to 300 keV) in order to form p-type layers with an Al plateau concentration of 4.5×1019 cm-3 and 9×1019 cm-3. Post-implantation annealing were performed at 1700 or 1800 °C up to 30 min in Ar ambient. During this process, some samples were encapsulated with a graphite (C) cap obtained by thermal conversion of a spin-coated AZ5214E photoresist. From Atomic Force Microscope measurements, the roughness is found to increase drastically with annealing temperature for unprotected samples while the C capped samples show a preservation of their surface states even for the highest annealing temperature. After 1800°C/30 min annealing, the RMS roughness is 0.46 nm for the lower fluence implanted samples, slightly higher than for unimplanted samples (0.31 nm). Secondary Ion Mass Spectroscopy measurements confirm that the C cap was totally removed from the SiC surface. The total Al-implanted fluence is preserved during postimplantation annealing. A redistribution of the Al dopants is observed at the surface which might be attributed to Si vacancy-enhanced diffusion. An accumulation peak is also observed after annealing at 0.29 9m, depth corresponding to the amorphous/crystalline interface that was determined on the as-implanted samples by Rutherford Backscattering Spectroscopy in channeling mode. The redistribution of the dopants has an impact on their electrical activation. A lower sheet resistance (Rsh= 8 k
) is obtained for samples annealed without capping than for samples annealed with C capping (Rsh= 15 k
).

Abstract: Low resistance p-layers are achieved in this paper using a graphite cap to protect SiC surface from out-diffusion of Si during high temperature post-implantation annealing, which is carried out to maximize the activation of Al dopant in 4H-SiC. With a graphite layer converted from photoresist, as high as 1700 and 1800oC post-implantation annealing is able to be used. Low RMS roughness of surface after high temperature annealing shows the effectiveness of the graphite cap. Small sheet resistance and resistivity are also achieved from the high temperature annealing. At room temperature, sheet resistances of 9.8 and 1.3 k
/□, and the corresponding resistivities of 235 and 31 m
-cm are obtained from 1700 and 1800oC annealed samples, respectively. The Al ionization energy extracted from Arrhenius plot is also close to the typical reported values. Therefore, it can be concluded that, using graphite cap could help to activate the Al dopant effectively during high temperature annealing.

Abstract: This work reports the realization and characterization of 4H-SiC p+/n diodes with the p+ anodes made by Al+ ion implantation at 400°C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6×1019 cm-3 and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600°C to 1700°C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 0-cm measured for the sample annealed at 1700°C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased, respectively, from 93% to 47% and from 2×10-7 Acm-2 to 1×10-8 Acm-2 at 100 V reverse bias, for increasing post implantation annealing temperature.

Abstract: An n-type 8° off-axis <0001> 4H-SiC epitaxial wafer was processed. The n-type epilayer had doping and thickness of, respectively, ~3 × 1015 cm-3 and ~5 μm. p+/n diodes with not terminated junctions were constructed by a selective area implantation process of 9.2 × 1014 cm-2 Al+ ions at 400°C. The diodes had areas in the range 2×10-4 -1×10-3 cm2. The Al depth profile was 6×1019 cm-3 high and 164 nm thick. The post implantation annealing process was done in a high purity Ar ambient at 1600°C for 30 min. The diode current-voltage characteristics were measured in the temperature range 25-290°C. Statistics of 50-100 measurements per device type were done. The fraction of diodes that could be modeled as abrupt junctions within the frame of the Shockley theory decreased with increasing area value, but was always > 75%. The ideality factor was > 2 only at temperatures > 200°C and bias values < 1 V. The leakage current was extremely weak and remained of the order of 10-9 Acm-2 at 70°C and 500 V reverse bias. 4% of the diodes reached the theoretical voltage breakdown that was 1030 V. The surface roughness of un-implanted and implanted regions after diode processing was, respectively, 2 nm and 12 nm.

Abstract: We developed EBAS-100, which is available to 100 mm diameter SiC wafer, for post ion implantation annealing in order to realize silicon carbide (SiC) device with large volume production. EBAS-100 is able to perform the rapid thermal process due to the vacuum thermal insulation and small heat capacity of susceptor. Electrical power consumption density was 18.8 Wh/cm2 for EBAS-100, which is one-third smaller than that of our previous system (EBAS-50). Samples used in this study were p-type epitaxial 4H-SiC (0001) grown on 8o off SiC substrate. P+ ions (total dose; 2.0 x 1016 /cm2, thickness; 350 nm) were implanted into SiC samples at 500 oC. The root-mean-square (RMS) of surface roughness is estimated to be 0.21 nm for the sample annealed at 1700 oC for 5 min, which is much smooth than that of the sample annealed by the conventional RF inductive annealing (RMS value: 5.97 nm). Averaged sheet resistance (RS) value of 63.3 ohm/sq. is obtained with the excellent non-uniformity of RS (+/- 1.4 %) for the diameter of 76.0 mm.