Papers by Keyword: Sidewall

Abstract: 3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

Abstract: Liquefied natural gas (LNG) is obtained by cooling the gas temperature to -162 degree. Problems with the steel cans, the insulation layer or the concrete tank of the LNG tank can lead to changes of the temperature, local temperature decreases, and the safety of the tank is threatening. Through the combination of many sets of infrared thermal imager to monitor the temperature of the LNG storage tank’s sidewall, analyze the heat imagine, establish the corresponding relationship between the locations on the sidewall of the LNG tank and on the heat imagine, determine the position of the temperature point on the tank wall. Infrared thermal imaging technique for the sidewall of LNG storage tank can find out the heat abnormal conditions and fixing the temperature drop area in time, and provide powerful guarantee for the safe storage of the liquefied natural gas.

Abstract: Guaranteeing the reliability of gate oxides is one of the most important topics to realize regarding the SiC power MOSFET. In the case of trench MOSFET, since the gate oxides are formed on the trench sidewall, the damage and roughness on the trench sidewall can affect the lifetime of the gate oxides. Generally speaking, damage removal treatment is processed after trench dry etching in most cases. In Si processes, sacrificial oxidation, H₂ anneal and CDE (Chemical Dry Etching) are adopted commonly. In the case of SiC processes, sacrificial oxidation, H₂ anneal, and SiH₄/Ar anneal have been reported. Neverthless CDE which applied to SiC trench MOSFET has few precedents. We clarified the effect of CDE as a damage removal process. CDE has the effect of flattening the trench sidewall, and CDE makes the lifetime of gate oxides improve. CDE is an effective process for the reliability of SiC trench MOSFET.

Abstract: This paper presents deep-hole etching process by inductively coupled plasma (ICP),the hole is higher than 400um ,and its diameter is 200um wide. Etching process successfully used in anchor fabrication below 150 um deep in micro-inertial devices, is first used in deep-hole etching .The result is badly, the sidewall surface is coarse, and the sidewall perpendicularity is poor,the dimension difference between upper and down diameter is as large as 35um.Because with the depth increasing , deep-hole etching brings new problem, such as fluorine(F) radical and ions distributing very differently between in down and upper area, also extracting reactant and temperature distribution . To solve above problems, process parameters such as gas flow mass and time in one reaction cycle, source and substrate power, reaction pressure and temperature should be adjusted. Through several experiments, optimal process is applied and the result is satisfied .From SEM figure, The the sidewall surface is smoother, the sidewall perpendicularity is good, the dimension difference between upper and down diameter is controlled in 1.6um,the sidewall angle is 89.78°. The process has been used in deep-hole fabrication of micromachined filter, and the rate of device enhances largely at present.

Abstract: As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.

Abstract: Metrology plays an important role in the development and commercialisation of micro and nanotechnology. For calibrating versatile micro- and nanoscale standards, a dimensional metrology instrument coupled with multi sensor heads including atomic force microscope (AFM), tactile stylus, laser focus sensor and assembled cantilever probes (ACPs) has been developed. Two kinds of ACPs are highlighted in the paper. One is fabricated by gluing a vertical AFM cantilever to a horizontal AFM cantilever using micro assembling techniques. It is applicable for direct and non-destructive measurements of sidewall surfaces. The other is an ACP ball probe designed for true 3D measurements of micro structures. It is realised by gluing a tungsten wire with a probing sphere ball, 40 ... 120 µm in diameter, to a horizontal AFM cantilever. The ACP ball probe has advantages such as small probing forces (<1µN) and high probing sensitivity. Some typical calibrations on micro and nano structures such as step height, grating and sphere calotte artefact are introduced.

Abstract: A reliable fabrication method for providing close spacing between the emitter mesa and the base contact metal of InP-based heterojunction bipolar transistor is disclosed. The silicon nitride sidewall was formed on the emitter electrode and mesa periphery. It was used as a mask for emitter mesa etching and also as an overhang to self-align the base contact with respect to the emitter mesa. The self-aligned device fabricated by this technique exhibited better high-frequency performances with fT of 138 GHz and fmax of 143 GHz, respectively, superior to the re-aligned one on the same epitaxy wafer.