Papers by Keyword: Wet Chemical Etching

Abstract: Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system in package, and wafer level packaging applications. In this study, a wet chemical etching (WCE) process has been employed to enhance the sidewall quality of TSVs fabricated using nanosecond (ns) laser pulses. Experimental results show that the TSV sidewall roughness can be markedly reduced, from micrometer scale to nanometer scale. We concluded that the proposed method would enable semiconductor manufactures to use ns laser drilling for industrial TSV fabrication as the desired TSV sidewall quality can be achieved by incorporating the WCE process, which is suitable for mass production.

Abstract: The dislocations in electron-irradiated c-plane n-GaN epitaxial layers grown on c-plane sapphire substrates by MOCVD were revealed by several different wet chemical etching methods. And the defect-selective etching method combined with SEM was carried out to study the mechanism of dislocations generation of GaN. SEM images of GaN epilayers with several individual methods are in good agreement with each other. Among all the defects, threading dislocations (TDs) dominated in the GaN epilayers and these defects could be divided into three types. In addition, the EPDs after annealing at various temperatures were studied. The experimental results showed that suitable thermal annealing can eliminate some dislocations.

Abstract: (Pb, La) (Zr, Ti)O₃ (PLZT) antiferroelectric thick films were deposited on Pt (111)/ Ti/SiO₂/Si (100) substrates via sol-gel process. X-ray diffraction (XRD) analysis indicated that the films derived on Pt (111)/ Ti/SiO₂/Si (100) substrates showed strong (111) preferred orientation. The Bulk and Surface silicon of micromachining process were employed in the silicon-based antiferroelectric thick film microcantilever fabrication, such as wet chemical etching for PLZT, inductive couple plasmas (ICP)for silicon etching, platinum etching and so on. Challenges such as Pt/Ti bottom electrode and morphology of PLZT thick film were solved, the integration of functional antiferroelectric materials and MEMS technology, provide a new way of thinking for the design and manufacture of micro-actuators.

Abstract: Silicon nanowire transistor (SiNWT) was fabricated by using a silicon nanowire as a channel which directly connected to the source (S) and drain (D). In this work, a side gate (G) formation was used to develop a transistor structure. AFM lithography was performed to create the nanoscale oxide patterns via local anodic oxidation (LAO) mechanism. A conductive AFM tip was used to grow localized oxide layer on the surface of silicon on insulator (SOI) substrate by the application of voltage between tip and substrate. Other parameters that will influence the patterning process such as tip writing speed, relative air humidity, anodization time and substrate orientation were controlled. The patterned structure was etched with tetramethylammonium hydroxide (TMAH) and hydrogen fluoride (HF) acid to remove the uncovered silicon layer and silicon oxide mask patterns, respectively. The surface topography and dimension of the fabricated SiNWT was observed under AFM. Obtained results for the channel thickness, channel length and the distance between the channel and side gate are 32.92 nm, 7.63 µm and 108.07 nm, respectively. Meanwhile, the I-V characteristics of fabricated SiNWT measured at positive gate voltages are similar to p-type FET characteristics.

Abstract: Wet chemical etching with dry metal deposition method has been developed to fabricate large-area aligned silicon nanowire (SiNW) arrays. The combination of nanoclusters Ag film with proper interconnection and interspaces (of about 20 nm thick), and proper temperature during etching (from 20 to 80 °C) is vital to successfully fabricating large-area uniform SiNW arrays. Raman and photoluminescence spectra of the SiNW arrays indicated their potential applications in chemical detection and optical devices ,respectively.