Papers by Keyword: Wet Strip

Abstract: The purpose of this paper is to study the effects of wet strip clean for metal void reduction in trench first metal hard mask back end of line (BEOL) integration process in 14 nm Technology. A thicker TiN film is becoming important to resolve via-metal short yield and time-dependent dielectric breakdown (TDDB) issues caused by the Litho-Etch-Litho-Etch (LELE) misalignment due to smaller patterning features. This brings the multitude of advanced integration technology need for complete TiN hard mask (HM) removal, post etch residue removal, ultra low-k dielectric (ULK) and Cu stability, interconnect resistance, and continuing high volume manufacturing (HVM) cost challenges together with environmental concerns and the waste handling/treatment cost. At GlobalFoundries, we achieved a wet strip clean process with a 45 % lower cost of ownership (CoO) while maintaining the TiN HM removal rate, baseline critical dimension (CD), normalized defect density (DOI), the ULK and Cu stability, via resistance, and yield.

Abstract: In back-end of line processing, the polymer deposited on the dielectric sidewalls during the etch must be removed prior to subsequent processing steps to achieve high adhesion and good coverage of materials deposited in the etched features [1,. Typically, this is done by a combination of short plasma treatment and diluted wet clean, or by wet cleans alone. On the one hand, for porous dielectric stacks, a mild plasma treatment that preserves the integrity of the low-k dielectrics would not be sufficient to efficiently remove this residue. Furthermore, aqueous cleaning solutions is not efficient to achieve a complete removal without etching the underlying layer. Hence appropriate wet clean chemistries are needed to dissolve/decompose these polymers without etching the dielectric. On the other hand, analytical techniques available for direct characterization of sidewall polymer are limited. For a fast screening of potential chemistries capable of dissolving/removing polymer residues generated during the low-k etch, a fluoropolymer deposited on a blanket, checkerboard low-k substrate was used as a model polymer. In our recent study [, using X-ray photoelectron spectroscopy (XPS), it was shown that the polymer was composed of CF, CF₂, and CF₃ groups. This model polymer was found to be very similar to the polymer residue generated during the etch of the low-k stack using similar plasma. The present study mainly focused on the effect of UV treatment and the concentration of active component in wet clean solution on the structure change of the polymer and the enhancement of polymer removal.

Abstract: In Back-End-of-Line processing, the remaining photoresist layer after plasma etch is traditionally removed using a plasma process. Plasma process was reported to induce damage to porous dielectric [1-3]. To minimize damage to low-k material, wet alternative methods of removal of photoresist layer on porous low-k dielectrics are gaining a renewed interest [4]. However, the presence of a “crust” generated by etch plasma at the photoresist surface makes it impossible to completely remove by a pure organic solvent. Indeed, the crust, most likely composed of crosslinked polymer, is not soluble in organic solvents [5]. For this reason, a UV pre-treatment is investigated to break cross-links in the crust or to modify the crust to enhance removal efficiency with solvent stripping in more advanced generations.

Abstract: Ion implantation is one of many critical processes in the fabrication of semiconductor devices. While device geometries have been shrinking, the implant dose has typically been increasing. Historically, photoresist removal has been achieved through a combination of plasma “ashing” and a subsequent wet clean, often using a mixture of sulfuric acid and hydrogen peroxide at elevated temperature. The “piranha” or SPM strip is often followed by an ammonia based clean such as APM to remove particles and sulfate residues from the device. However, device constraints are presently having difficulty accommodating the film loss, surface roughening, high molecular temperatures and hot electron injection which may accompany a plasma ash. [1] The APM clean is also having to undergo modification in order to minimize oxide loss which would adversely affect device performance.

Abstract: A layer of hardened material (crust) forms on the surface of photo resist (PR) during the implantation. This crust can be described as highly cross-linked polymer [1, 2]. Its thickness and composition depends on the type of PR, implant species, energy, dose, temperature during implantation and other factors. The crust is very resistant against chemical attack. Its chemical resistance tends to increase with the continuous shrink of technology nodes as implant doses increase. Moreover, even small residues of PR, left after cleaning, become more critical with shrinking device geometry. The usual process sequence for stripping a PR after high dose implantation (HDI) is a plasma strip (PS) followed by a wet clean. The drawback of plasma ashing is increased substrate loss and dopant bleach [3]. Plasma strip or plasma ash stand in this paper for the approach of complete PR consumption in the plasma process. Wet stripping alone often is not sufficient for stripping PR after implant doses of ≥ 1x1015 ions/cm2.

Abstract: NiPt self-aligned silicide (salicide) has become a major candidate for the 45nm node due to its better thermal stability and the surface morphology of NiSi on Si substrate [1,2]. SiGe has been proposed for PMOS strain engineering [3]. The relevant SiGe oxidation behavior [4], reaction with platinum [5] and thermal stress behavior [6] are important factors in developing a process for 45nm NiPt salicide over SiGe stressor. These concerns require the review of the current process for NiPt to verify its compatibility and extendibility.