The Realization of Rapid Median Filter Algorithm on FPGA

En Shun Kang; Yu Xi Zhao

doi:10.4028/www.scientific.net/AEF.6-7.659

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HomeAdvanced Engineering ForumAdvanced Engineering Forum Vols. 6-7The Realization of Rapid Median Filter Algorithm...

The Realization of Rapid Median Filter Algorithm on FPGA

Abstract:

Traditional median filter algorithm has the long processing time, which goes against the real-time image processing. According to its shortcomings, this paper puts forward the rapid median filter algorithm, and uses DE2 board of the company called Altera to do the realization on FPGA (CycloneII 2C35). The experimental results show that the image pre-processing system is able to complete a variety of high-level image algorithms in milliseconds, and FPGA's parallel processing capability and pipeline operations can dramatically improve the speed of image processing, so the FPGA-based image processing system has broad prospects for development．

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Periodical:

Advanced Engineering Forum (Volumes 6-7)

Pages:

659-664

DOI:

https://doi.org/10.4028/www.scientific.net/AEF.6-7.659

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Online since:

September 2012

Authors:

En Shun Kang, Yu Xi Zhao

Keywords:

Field-Programmable Gate Array (FPGA), Image Preprocessing, Median Filter, Parallel Processing

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Creative Commons CC BY 4.0

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