A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme

Abstract:

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Combined with partial dynamic threshold MOSFET connection scheme, a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper. Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation. The 7T SRAM exhibits robust efficiency, making the design less vulnerable to process variation. Compared to the referenced 6T and the 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.1% and 6.1% larger hold margin, (2) 80.6% and 85.5% of standard deviation, (3) 50% and 18% reduction of area (at 200 mV), and (4) 16X and 32X bitcells per bitline. To our best knowledge, the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

Info:

Periodical:

Edited by:

Dongye Sun, Wen-Pei Sung and Ran Chen

Pages:

1279-1285

DOI:

10.4028/www.scientific.net/AMM.121-126.1279

Citation:

J. Yang et al., "A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme", Applied Mechanics and Materials, Vols. 121-126, pp. 1279-1285, 2012

Online since:

October 2011

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$35.00

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