Design and CMOS Implementation of a Low Power System-on-Chip Integrated Circuit

Abstract:

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A low power 32-bit microcontroller using different kinds of low-power techniques to adapt to the dynamically changing performance demands and power consumption constraints of battery powered applications is designed and tested. Four power domains and six power modes are designed to fulfill low-power targets and meet different functional requirements. Varieties of low power methods such as dynamic voltage and frequency scaling (DVFS), multiple supply voltages (MSV), power gating (PG) and so on are applied. A novel zero steady-state current POR circuit which makes excellent performance in the chip’s OFF mode is also integrated. The SoC occupies 20 mm2 in a 0.18 um, 1.8 V nominal-supply, CMOS process. Test results show that the microcontroller works normally at the frequency of 70MHz and performs well in different power modes. Yet it only consumes 1.67μA leakage current in the OFF mode.

Info:

Periodical:

Edited by:

Dongye Sun, Wen-Pei Sung and Ran Chen

Pages:

755-759

DOI:

10.4028/www.scientific.net/AMM.121-126.755

Citation:

H. L. Gu et al., "Design and CMOS Implementation of a Low Power System-on-Chip Integrated Circuit", Applied Mechanics and Materials, Vols. 121-126, pp. 755-759, 2012

Online since:

October 2011

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Price:

$35.00

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