Design and CMOS Implementation of a Low Power System-on-Chip Integrated Circuit

Abstract:

A low power 32-bit microcontroller using different kinds of low-power techniques to adapt to the dynamically changing performance demands and power consumption constraints of battery powered applications is designed and tested. Four power domains and six power modes are designed to fulfill low-power targets and meet different functional requirements. Varieties of low power methods such as dynamic voltage and frequency scaling (DVFS), multiple supply voltages (MSV), power gating (PG) and so on are applied. A novel zero steady-state current POR circuit which makes excellent performance in the chip’s OFF mode is also integrated. The SoC occupies 20 mm2 in a 0.18 um, 1.8 V nominal-supply, CMOS process. Test results show that the microcontroller works normally at the frequency of 70MHz and performs well in different power modes. Yet it only consumes 1.67μA leakage current in the OFF mode.

• Periodical: Applied Mechanics and Materials (Volumes 121-126)
• Pages: 755-759
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.121-126.755
• Online since: October 2011
• Authors: Hao Lin Gu, Wei Wei Shan, Yun Fan Yu, Yin Chao Lu
• Keywords: Low Power, Power on Reset (POR), System on Chip (SoC)

References

[1] K. Usami et al.: Automated Low-power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor. Proc. IEEE Custom Integrated Circuits Conference (1997) pp.131-134.

DOI: 10.1109/cicc.1997.606600

[2] L. Chandrasena, P. Chandrasena, and M. Liebelt: An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling. Proc. ISSS (2001) p.124–129.

DOI: 10.1145/500001.500031

[3] A. Mukheijee et al.: Clock and Power Gating with Timing Closure. Design & Test of Computers, IEEE vol. 20, no. 3 (2003).

DOI: 10.1109/mdt.2003.1198683

[4] P. Royannez et al.: 90 nm low leakage SoC design techniques for wireless applications. IEEE ISSCC'2005 Dig., San Francisco, CA (2005), p.138–139.

[5] Phillip E Allen, Douglas R Holberg: CMOS analog circuit design. Second Edition. Beijing: Publishing House of Electronics industry (2002), pp.149-154.

[6] R. Gonzalez, B. Gordon, and M. Horowitz: Supply and threshold voltage scaling for low power CMOS [J]. IEEE J. Solid State Circuits, vol. 32(2000), p.1210–1216.

DOI: 10.1109/4.604077

[7] S.K. Wadhwa et al.: Zero steady state current power-on-reset circuit with Brown-out detector. Proceedings of the IEEE International Conference on VLSI Design (2006), pp.631-636.

DOI: 10.1109/vlsid.2006.172