Implementation of DES Encryption Algorithm Based on FPGA and Performance Analysis

Abstract:

This paper introduced the principle of DES encryption algorithm, designed and realized the DES encryption algorithm with verilog hardware description language, realized module simulation with Quartus II. Two comprehensive considerations from the resources and performance, one pipeline stage control is set in round function to improve the processing speed, Synchronous pipeline architecture of data XOR key round function and Key transformation function is realized on hardware to reducing logic complexity of the adjacent pipeline, round function multiplexing is realized by setting the round counter and controlling the data selector.

• Periodical: Applied Mechanics and Materials (Volumes 130-134)
• Pages: 2953-2956
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.130-134.2953
• Online since: October 2011
• Authors: Ji Hong Lian, Kai Chen
• Keywords: Data Encryption, DES Algorithms, Field-Programmable Gate Array (FPGA), Pipeline, Verilog HDL

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