FPGA Based Testing Method to Improve Digital IC Testability

Yin Shui Gong; Hui Yun Li

doi:10.4028/www.scientific.net/AMM.130-134.3920

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 130-134FPGA Based Testing Method to Improve Digital IC...

FPGA Based Testing Method to Improve Digital IC Testability

Abstract:

With the development of integrated circuit technology, design for test (DFT) is on the agenda. In this paper, we propose a new method that the non-test part of a SIP chip can be easily tested with the boundary-scan test utilizing the boundary scan chain of the FPGA. The problem of no boundary scan test structure in one (or more) chip in a system-in-package (SIP) can be solved by connecting the interconnection (s) to be tested to the FPGA to form an enlarged boundary scan daisy chain.

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Periodical:

Applied Mechanics and Materials (Volumes 130-134)

Pages:

3920-3923

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.130-134.3920

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Online since:

October 2011

Authors:

Yin Shui Gong, Hui Yun Li

Keywords:

Boundary Scan, Controllability/Observability, Field-Programmable Gate Array (FPGA)

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References

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