FPGA Based Testing Method to Improve Digital IC Testability
With the development of integrated circuit technology, design for test (DFT) is on the agenda. In this paper, we propose a new method that the non-test part of a SIP chip can be easily tested with the boundary-scan test utilizing the boundary scan chain of the FPGA. The problem of no boundary scan test structure in one (or more) chip in a system-in-package (SIP) can be solved by connecting the interconnection (s) to be tested to the FPGA to form an enlarged boundary scan daisy chain.
Y. S. Gong and H. Y. Li, "FPGA Based Testing Method to Improve Digital IC Testability", Applied Mechanics and Materials, Vols. 130-134, pp. 3920-3923, 2012